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[executorch][cuda] Route 3-input-channel window and kernel-equals-stride convolutions to the implicit-GEMM template - #25087
On convolutions with 3 input channels, Inductor's Triton conv template spends most of each channel block on empty lanes. The implicit-GEMM template walks the 3 channels without them, but no call is routed to it.
worth_routing now takes 3-channel calls whose (kernel, stride, symmetric padding) is in ROUTED_FAMILIES: 3x3, 5x5 and 7x7 windows with stride 1, 2 or 4 and padding 0 or half the kernel, 2-D convolutions with kernel == stride from 2 to 32, and 3-D ones with kernel == stride (1,4,4), (2,14,14) and (2,16,16). It bounds batch, extent, input pixels, output pixels, output channels and output elements, and requires a dense NCHW or channels-last input, a contiguous weight, and tensor cores for fp16, bf16 and TF32. Everything else, 1x1 convolutions included, keeps the regular lowering with a recorded reason. benchmarks/conv/benchmark_implicit_gemm.py measures boundary_calls(), every family geometry at every corner of these limits: all 224 are significantly faster than Inductor on an A100 in fp32, fp16, bf16 and TF32, with NCHW and channels-last inputs. The benchmark also has shapes and envelope suites.
test_conv_routing.py derives its range tests from boundary_calls(): every corner routed, one step past each limit and unbenchmarked layouts kept. test_conv_implicit_gemm.py lowers routed models and runs them against eager.
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Stack from ghstack (oldest at bottom):
On convolutions with 3 input channels, Inductor's Triton conv template spends most of each channel block on empty lanes. The implicit-GEMM template walks the 3 channels without them, but no call is routed to it.
worth_routingnow takes 3-channel calls whose (kernel, stride, symmetric padding) is inROUTED_FAMILIES: 3x3, 5x5 and 7x7 windows with stride 1, 2 or 4 and padding 0 or half the kernel, 2-D convolutions with kernel == stride from 2 to 32, and 3-D ones with kernel == stride (1,4,4), (2,14,14) and (2,16,16). It bounds batch, extent, input pixels, output pixels, output channels and output elements, and requires a dense NCHW or channels-last input, a contiguous weight, and tensor cores for fp16, bf16 and TF32. Everything else, 1x1 convolutions included, keeps the regular lowering with a recorded reason.benchmarks/conv/benchmark_implicit_gemm.pymeasuresboundary_calls(), every family geometry at every corner of these limits: all 224 are significantly faster than Inductor on an A100 in fp32, fp16, bf16 and TF32, with NCHW and channels-last inputs. The benchmark also hasshapesandenvelopesuites.test_conv_routing.pyderives its range tests fromboundary_calls(): every corner routed, one step past each limit and unbenchmarked layouts kept.test_conv_implicit_gemm.pylowers routed models and runs them against eager.This diff was authored with Claude Code.
Differential Revision: D129645242
NOTE FOR REVIEWERS: This PR has internal Meta-specific changes or comments, please review them on Phabricator!