[Gasoonjia]

Stack from ghstack (oldest at bottom):

• [executorch][cuda] Run transposed convolutions on the implicit-GEMM template #25091
• [executorch][cuda] Test 3-D convolutions on the implicit-GEMM template #25090
• [executorch][cuda] Run 1-D convolutions on the implicit-GEMM template #25089
• [executorch][cuda] Converted convolutions follow the output layout the graph recorded #25088
• [executorch][cuda] Route 3-input-channel window and kernel-equals-stride convolutions to the implicit-GEMM template #25087
• -> [executorch][cuda] Add an implicit-GEMM template for dense triton::convolution #25086
• [executorch][cuda] Route 2-D depthwise and few-channel grouped convolutions to a Triton direct-stencil kernel #25085
• [executorch][cuda] Add triton::convolution and the conv routing framework #25084
• [executorch][cuda] Add planned replacement to the Triton replacement pass #25083
• [executorch][cuda] Deprecate triton_kernel_mode=OFF #25082

Dense convolutions have no triton::convolution template, so calls Inductor cannot compile have nowhere to go, and convolutions on which Inductor's template wastes work, such as 3-channel inputs whose channel blocks are mostly empty, cannot be improved.

This diff adds an implicit-GEMM template for dense (groups 1) 2-D and 3-D forward convolutions. One kernel is written for (D, H, W), lower ranks being unit dims; shapes and geometry are constexpr, so bounds checks the geometry cannot fail compile away. K is walked per kernel tap in blocks of input channels from 16 channels, and as one flat (channel, tap) index below that, which wastes no lanes on 3-channel inputs. Two schedules are timed at compile time: igemm_ffma (FP32 FMA, portable) and igemm_tc (tensor cores for fp16/bf16, TF32 for fp32; sm_80). conv_allows_tf32() follows the TF32 setting of Inductor's conv templates, so a convolution keeps its precision whether it is routed or not. No call is routed yet.

test_conv_implicit_gemm.py runs every schedule, K order and config against an FP64 reference over representative geometries, dtypes, layouts, biases, sliced inputs and a 2^31-element input, and checks the capability and TF32 gates of the tensor-core schedule.

This diff was authored with Claude Code.

Differential Revision: D129645280

NOTE FOR REVIEWERS: This PR has internal Meta-specific changes or comments, please review them on Phabricator!

[pytorch-bot]

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✅ You can merge normally! (2 Unrelated Failures)

As of commit 4ce2697 with merge base dea39f0 ():

BROKEN TRUNK - The following jobs failed but were present on the merge base:

👉 Rebase onto the `viable/strict` branch to avoid these failures

• Test CUDA Builds / test-muse-glimmer-cuda-e2e-kquant-17gb-dflash-image-batching / linux-job (gh) (trunk failure)
  ##[error]received SIGINT
• Test ROCm AOTI / test-voxtral-realtime-rocm-gfx950-rocm7.2 / linux-job (gh) (trunk failure)
  ##[error]The operation was canceled.

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