docs(cubie a7z): clarify MIPI CSI only supports single 4-lane#1898
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Milir-Radxa merged 2 commits intoJul 1, 2026
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The previous text claimed the board supported '1x 4-lane or 2x 2-lane' MIPI CSI, but the v1.10 schematic only brings out one MIPI clock lane (J5 CAM_31P pin 17/18) on the camera FPC connector; the second clock position (pin 8/9) is NC. Drop the 2x 2-lane claim so the docs match the actual hardware.
…E spec table Same fix as the previous commit on the dedicated MIPI CSI page: the A7Z only exposes one MIPI clock lane on the camera FPC (J5 pin 17/18), so the 4 data lanes cannot be split into two independent 2-lane cameras. Remove the split claim from the A7Z README spec table to match.
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Milir-Radxa
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Same correction as the A7Z docs in PR #1898. The v1.10 schematic (page 11, CAMERA) shows that connector J7 (CAM_31P) only brings out one MIPI clock lane (pin 18/19, net MCSIB-CKN/CKP). The second clock position (pin 9/10, MIPI_CLKBN/BP) is NC. With only one MIPI clock on the connector, the 4 data lanes cannot be split into two independent 2-lane cameras. Remove the split claim from the spec table and the MIPI CSI page so the docs match the hardware.
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Summary
Drop the "or two 2-lane MIPI CSI" wording in the Cubie A7Z MIPI CSI page so the docs match the actual hardware.
Background
The previous text claimed the board supports
1x 4-lane or 2x 2-laneMIPI CSI. Reviewingradxa_Cubie_A7Z_v1100_schematic.pdf(page 10,CAMERA) showed that the camera FPC connector J5 (CAM_31P) only brings out one MIPI clock lane (pin 17/18, netMCSIB-CKN/CKP). The second clock position (pin 8/9,MIPI_CLKBN/BP) is marked NC. With only one MIPI clock on the connector, the 4 data lanes cannot be split into two independent 2-lane cameras.Changes
docs/cubie/a7z/hardware-use/mipi-csi.md(zh)i18n/en/docusaurus-plugin-content-docs/current/cubie/a7z/hardware-use/mipi-csi.md(en)Both now read "1 个 4 通道 MIPI CSI 接口" / "one 4-lane MIPI CSI interface".
Scope
docs-only, two files, one sentence per file. No code, no image, no schema change.
Checklist
python3 scripts/github_pr_guard.py checkokupstream-docs/main(radxa-docs/docs)