fix(gen-verilog-sim): test-block reg declarations + 64-bit __mul_noop - #1899
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…bench prelude
Named test-block bindings ('h = f(...);') parse as StmtAssign, not
StmtLocal, so gen_verilog_probe_prelude never declared them and iverilog
could not bind the names -- 21 of tri-net's 26 lowerable ring specs failed
to compile. Declare every plain-identifier assign target once, recursively
collected, width-inferred from its value expression (64-bit fallback),
before any procedural statement. Unlocks 11 of the 21 immediately (the
rest hit the u64 __mul_noop truncation, #1886).
FROZEN_HASH resealed per ceremony.
Closes #1894
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-08-07 19:49:27 UTC
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…runcate The injected R-SI-1 multiplication helper was function [31:0] with [31:0] inputs, so every u64 multiply in generated Verilog silently truncated -- GF-T32/64 mantissa products (up to 2^48+) computed wrong in simulation while the same spec functions are correct in gen-rust and in the hand-written silicon KATs. Now [63:0] in/out with a [127:0] accumulator over 64 iterations; 32-bit callers are unchanged (zero-extended). Unlocks tri_gft_arith and the u64 money-layer specs in tri-net's icarus KAT run. FROZEN_HASH resealed. Closes #1886 Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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Two testbench-path fixes, each surfaced by running tri-net's ring specs under the new icarus KAT flow:
Closes gen-verilog-sim: test-block local bindings emitted as assignments without reg declarations #1894 -- named test-block bindings (
h = f(...);) parse as StmtAssign, not StmtLocal, sogen_verilog_probe_preludenever declared them and iverilog could not bind the names (21 of 26 lowerable tri-net ring specs failed to compile). Every plain-identifier assign target is now declared once (recursively collected, width-inferred from the value expression, 64-bit fallback) before any procedural statement.Closes gen-verilog: u64 width truncation in lowered helper functions (surfaced by icarus assert lowering) #1886 -- the injected R-SI-1
__mul_noophelper wasfunction [31:0]with[31:0]inputs: every u64 multiply silently truncated, so GF-T32/64 mantissa products computed wrong in simulation while gen-rust and the silicon KATs are correct. Widened to[63:0]in/out with a[127:0]accumulator over 64 iterations; 32-bit callers unchanged.Validation: on tri-net's ring specs the icarus run goes 5/26 -> 23/26 locally (the last three blockers are tri-net spec-side: Verilog reserved words
class/smallused as identifiers, and one stale spec test the simulation legitimately catches -- fixed in tri-net separately). FROZEN_HASH resealed per ceremony; NOW.md updated.🤖 Generated with Claude Code