docs: endpoint reg insufficient (internal hazard); MMCM divided clock buildable + ruled-out list (Refs #1764) - #1902
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… buildable (Refs #1764) Variant 2 (discriminating cheap test): registering the shared-core endpoints (FF operands a_reg/b_reg in, FF result res_reg out) is bit-exact in sim and raises fmax 21->29 MHz, but on silicon does NOT fix the seed-lottery (of 4 seeds: 2 dead routes, 2 glitch from ep0). So the hazard lives inside the depth-54 GftSadd cloud; only the spec-level mid-cascade pipeline closes it. Variant 3 probe: a real divided clock IS buildable via MMCM (MMCME2_BASE places on a real MMCME2_ADV bel by dedicated routing), unlike fabric BUFG/BUFR — but by the endpoint result it only adds settle, so it stays a bounded experiment behind the pipeline. Added a consolidated "Ruled-out fixes" list. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Superseded by #(new) rebased on master (NOW.md conflict with #1899 resolved); no force-push. |
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Executes the three follow-ups from the last cycle ("все три"):
Variant 2 — endpoint registration (the discriminating cheap test). Register the shared core's endpoints (clean FF operands
a_reg/b_regin, FF resultres_regout) without splitting the deep cloud. Bit-exact in simulation (ep0 = 0 / 0.551 / 0.936 / 0.234 matches the model) and it even raised fmax 21 → 29 MHz by pullingmodfout of the core path. But on the AX7203, of 4 seeds two produced dead routes and two glitched from ep0 (explode/collapse) — same as baseline. Conclusion: resynchronising the boundaries is insufficient; the fault lives inside the depth-54GftSaddcloud, so only the spec-level mid-cascade pipeline closes it. The cheap wrapper fix is ruled out.Variant 3 — MMCM probe + ruled-out list. A real divided clock is buildable via
MMCME2_BASE(nextpnr constrains it to a realMMCME2_ADVbel by dedicated routing and routes the divided output as a genuine clock), unlike fabricBUFG/BUFR. By the Variant-2 result it only adds settle, so it stays a bounded experiment behind the pipeline. Added a consolidated Ruled-out fixes list (wider settle, more settle, tighter timing, fabric divided clock, observability probe, narrowing the multiplier, endpoint registration) so future cycles don't re-run dead ends.Board restored to the generated capstone (XOR 4/4). Docs-only. Refs #1764