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spec: legalize Verilog-reserved identifiers + fix a stale tri_a2a test; icarus KAT runs all 30 lowerable specs - #310

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Aug 7, 2026
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spec: legalize Verilog-reserved identifiers + fix a stale tri_a2a test; icarus KAT runs all 30 lowerable specs#310
gHashTag merged 1 commit into
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spec/verilog-reserved-and-stale-test

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@gHashTag gHashTag commented Aug 7, 2026

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With upstream gHashTag/t27#1899 merged (test-block reg declarations + 64-bit __mul_noop), the last three icarus blockers were tri-net spec bugs:

  • Verilog reserved words as identifiers broke the generated testbenches: tri_a2a_wire (class -> msg_class), tri_compute_bitnet (packed -> packed_w), tri_depin (small -> small_acc).
  • A stale spec test the simulation legitimately caught: tri_a2a's hosted_skill_set still asserted 0xA511 is NOT hosted -- but 0xA511 is SKILL_GFT32_MUL and IS hosted (the test predates the GF-T32 skills and had never been executed anywhere until the icarus flow ran it). Now asserts on 0xA512, an unknown-op id.

The gft-verilog-kat run grows 8 -> 30 specs: every icarus-lowerable ring spec (crypto_frame and discovery are not lowerable) now executes its spec test blocks in simulated hardware on every relevant PR -- the full money layer (settle/ledger/merkle/payout/pool/bond/reputation), the crypto root (tri_sha256), A2A, transport (fec/ilv), and all four GF-T arithmetic specs including the previously u64-blocked tri_gft_arith. Local validation: 30/30 sim pass, full cargo gate ok.

🤖 Generated with Claude Code

…t; icarus KAT runs all 30 lowerable specs

Three specs used Verilog/SystemVerilog reserved words as identifiers, which
broke their generated testbenches: tri_a2a_wire ('class' -> msg_class),
tri_compute_bitnet ('packed' -> packed_w), tri_depin ('small' -> small_acc).
tri_a2a's hosted_skill_set test still asserted 0xA511 is not hosted -- but
0xA511 is SKILL_GFT32_MUL and IS hosted; the test predates the GF-T32
skills and was never executed until the icarus flow ran it (now asserts on
0xA512, an unknown-op id). With upstream t27#1899 (test-local reg decls +
64-bit __mul_noop), every icarus-lowerable ring spec simulates clean;
the gft-verilog-kat run grows 8 -> 30 specs (crypto_frame and discovery
are not lowerable). Local validation: 30/30 sim pass, full cargo gate ok.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
@gHashTag
gHashTag merged commit 562a4b3 into main Aug 7, 2026
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@gHashTag
gHashTag deleted the spec/verilog-reserved-and-stale-test branch August 7, 2026 20:05
gHashTag added a commit that referenced this pull request Aug 8, 2026
…st-check clean (#322)

The gen-zig validity campaign (t27#1910, closed by #1911/#1915/#1917/#1918
plus tri-net's spec legalizations #310/#321) took the backend from 66/68
invalid to 0/68. gen/zig/ returns with all 68 files (each validated with
zig ast-check 0.15.2), and spec-drift-guard's Zig leg is back: byte-exact
diff against 't27c gen' built from upstream master (no formatter in the
Zig path, so no fmt-vs-drift contradiction). Two backends now under the
required drift gate.

gen/ additions are t27c generations (L2 bypassed per the guard's fix path).

Co-authored-by: SSD DDD <ssdm4@MacBook-Pro.local>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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