fix(gen-verilog-sim): lower plain assert(cond, "msg") to an if-based check - #1885
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…check 'assert' is not a Verilog-2005 keyword and the two-argument form is not SystemVerilog either, so the testbench emitted it verbatim and iverilog rejected the entire generated file -- icarus-simulate was unusable for any spec whose tests use assert() (the standard t27 form) rather than assert_eq(). Both emission paths (probed assertions and the W459 real-check path) now lower assert to the same if-based check assert_eq gets, with the %-escaped message in the failure display. Validation: bootstrap unit suite 1537/1537, identical to unmodified master; tri-net GF-T specs go from iverilog-reject to full runs (add/sub/ladder PASS; tri_gft_arith surfaces the pre-existing u64 width bug, #1886). FROZEN_HASH resealed and NOW.md updated per ceremony. Closes #1888 Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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New gft-verilog-kat workflow: t27c icarus-simulate generates a self-checking testbench from tri_gft_add / tri_gft_sub / tri_gft_ladder and runs it under iverilog -- the same specs that drive the Rust verifier and the synthesizable silicon now have their assertions executed on the Verilog path in CI. Requires t27c >= gHashTag/t27#1885 (assert lowering). tri_gft_arith stays out until the upstream u64 width bug (t27#1886) is fixed. Co-authored-by: SSD DDD <ssdm4@MacBook-Pro.local> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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assertis not a Verilog-2005 keyword and the two-argumentassert(cond, "msg")form is not SystemVerilog either, so the generated testbench emitted it verbatim and iverilog rejected the entire file --icarus-simulatewas unusable for any spec whose tests useassert()(the standard t27 form) rather thanassert_eq(). Both emission paths (the probed-assertions path and the W459 real-check path) now lowerassertto the same if-based checkassert_eqgets, with the message (%-escaped) in the failure display.Validation: bootstrap unit suite 1537 passed / 0 failed -- identical to unmodified master; the pre-existing
bitnet_layerintegration failure reproduces identically on unmodified master (unrelated). On tri-net's four GF-T specs,icarus-simulategoes from "iverilog rejected generated Verilog" to full runs: tri_gft_add / tri_gft_sub / tri_gft_ladder PASS end to end, and tri_gft_arith now SURFACES a real pre-existing failure (GF-T32 u64 helper tests -- u64 width truncation in gen-verilog, the same family as ff0b8de's gen-rust fix; filing separately).FROZEN_HASH updated per the FROZEN.md ceremony.
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Closes #1888