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feat: emit_verilog can emit the silicon-ready variant (clk_div) - #1889

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feat/emit-silicon-ready-clkdiv
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feat: emit_verilog can emit the silicon-ready variant (clk_div)#1889
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feat/emit-silicon-ready-clkdiv

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@gHashTag gHashTag commented Aug 7, 2026

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The capstone (full backprop trains XOR on live AX7203) ran on a hand-written board wrapper, not the CI-verified generator. This closes the gap: emit_verilog / emit_verilog_deep now take clk_div (default 1 = unchanged). clk_div>1 emits the silicon-ready variant — the exact fix that trains on silicon: register file forced to flip-flops (ram_style=registers, since distributed LUTRAM can't do the parallel weight init) + a /N clock-enable so the deep shared-core path gets ~clk_div×SETTLE cycles to settle (the open-source P&R can't express a multicycle constraint).

clk_div only changes timing, not values — verified bit-exact to the model in iverilog (clk_div=4, 12 training steps, RTL == model); default clk_div=1 is byte-identical to before, so the existing bit-exact/synth/datapath gate is unaffected (still ALL SYNTHESIZE). Self-test asserts the gating is emitted for clk_div=16 and absent for clk_div=1. The CI-verified generator now emits the same RTL that trains a neural net on real silicon — unifying the verification and silicon threads. Refs #1764

The capstone (full backprop trains XOR on live AX7203) ran on a hand-written board
wrapper, not the CI-verified generator. emit_verilog / emit_verilog_deep now take
clk_div (default 1 = unchanged). clk_div>1 emits the silicon-ready variant -- the
exact fix that trains on silicon: register file forced to flip-flops
(ram_style=registers, since distributed LUTRAM can't do the parallel weight init) +
a /N clock-enable so the deep shared-core path gets ~clk_div*SETTLE cycles to settle
(the open-source P&R can't express a multicycle constraint). clk_div only changes
timing, not values -- verified bit-exact to the model in iverilog (clk_div=4, 12
training steps); default clk_div=1 is byte-identical to before, so the existing
bit-exact/synth/datapath gate is unaffected. Self-test asserts the gating is emitted
for clk_div=16 and absent for clk_div=1. The CI-verified generator now emits the same
RTL that trains a neural net on real silicon.

Refs #1764

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-08-07 17:25:37 UTC

Summary

Status Count
Total Open PRs 14
PRs with Failing Checks 2
PRs with All Checks Green 12
READY 5
FAILING 2
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=4c1aaad5309a != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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PR Dashboard

Generated at: 2026-08-07 17:33:10 UTC

Summary

Status Count
Total Open PRs 13
PRs with Failing Checks 1
PRs with All Checks Green 12
READY 5
FAILING 1
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=f74459fc23c3 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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gHashTag merged commit dc2d6b7 into master Aug 7, 2026
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gHashTag deleted the feat/emit-silicon-ready-clkdiv branch August 7, 2026 17:39
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