ci(gft): execute GF-T spec test blocks under Icarus Verilog - #306
Merged
Conversation
New gft-verilog-kat workflow: t27c icarus-simulate generates a self-checking testbench from tri_gft_add / tri_gft_sub / tri_gft_ladder and runs it under iverilog -- the same specs that drive the Rust verifier and the synthesizable silicon now have their assertions executed on the Verilog path in CI. Requires t27c >= gHashTag/t27#1885 (assert lowering). tri_gft_arith stays out until the upstream u64 width bug (t27#1886) is fixed. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
New gft-verilog-kat workflow:
t27c icarus-simulategenerates a self-checking Verilog testbench from tri_gft_add / tri_gft_sub / tri_gft_ladder and runs it under iverilog in CI -- the same specs that drive the Rust verifier and the synthesizable silicon now have their test assertions executed on the Verilog path too. Enabled by gHashTag/t27#1885 (assert lowering, merged); local runs PASS end to end on all three. tri_gft_arith stays excluded until the upstream u64 width-truncation bug (gHashTag/t27#1886) is fixed -- that bug was itself surfaced by the new lowering.🤖 Generated with Claude Code