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amba-apb-transceiver
amba-apb-transceiver PublicAMBA APB Master-Slave protocol implementation in Verilog with zero-wait and wait-state support.
Verilog 1
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cache-controller-sram
cache-controller-sram Public2-way set-associative cache controller in Verilog with single-port SRAM interface.
Verilog 1
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cpp-for-digital-systems
cpp-for-digital-systems PublicParameterized C++ software simulator modeling N-way Cache architectures.
C++ 1
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uart-transceiver-verilog
uart-transceiver-verilog PublicParameterized UART transceiver in Verilog with baud generator and error handling.
Verilog 1
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verilog-rtl-design
verilog-rtl-design PublicSynthesizable Verilog RTL implementations and Digital Logic foundations.
Verilog 1
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vga-controller-sram
vga-controller-sram PublicVGA display controller in Verilog with SRAM frame-buffer interface.
Verilog 1
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