2-Way Set Associative Cache Controller

Project Overview

This repository features the RTL mapping and memory interface logic of a 2-way set-associative cache controller, engineered to perform high-speed access resolution against a dual-bank SRAM topology.

Core Architecture

graph LR
    CPU((CPU Memory Trace)) --> A[Cache Controller Interface]
    A -->|Tag/Index| B{Set Checker}
    B -->|Hit| C[SRAM Way 0]
    B -->|Hit| D[SRAM Way 1]
    C --> E[Data Output Mux]
    D --> E
    B -->|Miss| F[Eviction Logic]

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Design Decisions

• Way-Selection Logic: Valid bits integration within raw payload wrappers natively enforces write-enable flags against arbitrary index vectors to reduce combinatorial path delays.
• Static SRAM Instantiation: To maintain deterministic cycle behavior over dynamic memory generation, identical single_port_sram primitives are instantiated rigidly to serve independent logical mapped 'ways'.

Verification Operations

Run the functional testbench leveraging standard Verilog discrete clock manipulations:

iverilog -o cache_sim rtl/cache_controller.v tb/cache_controller_tb.v
vvp cache_sim

Engineering Concepts Demonstrated

• Hardware level associative memory resolving mappings.
• Data path propagation delay analysis for combinatorial read-assert blocks.
• Synchronous Multi-memory instantiations mimicking SoC behavior models.