A localized catalog of low-level C++ architectures supporting digital design, focusing exclusively on modeling hardware hierarchies in software. Features a complete set-associative cache simulator written utilizing core Object-Oriented principles, dynamic STL integration, and bitwise data decomposition (tag, index, and byte offset calculations).
/src/cache_simulator: A fully object-oriented cache simulator supporting LRU (Least Recently Used) replacement schemas./src/examples: Short standard-library integration examples covering hardware pointer manipulation.
The Cache Simulator demonstrates real-time address tagging against an integrated trace.txt memory payload.