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Sail Mailbox changes for dt-bindings & Devicetree Overlay #649

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Sail Mailbox changes for dt-bindings & Devicetree Overlay #649

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fdf6287
QCLINUX: dt-bindings: mailbox: qcom-ipcc: Add SAIL client IDs
snegi-qti Jun 3, 2026
7eebc3e
QCLINUX: arm64: dts: qcom: lemans: Add SAIL Mailbox device tree overlay
snegi-qti Jun 3, 2026
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1 change: 1 addition & 0 deletions arch/arm64/boot/dts/qcom/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -465,6 +465,7 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo

dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo
dtb-$(CONFIG_ARCH_QCOM) += lemans-sail-mb.dtbo

monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo

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65 changes: 65 additions & 0 deletions arch/arm64/boot/dts/qcom/lemans-sail-mb.dtso
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@@ -0,0 +1,65 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/

/dts-v1/;
/plugin/;

#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

&soc {
ipcc_computeL1: qcom,ipcc@488000 {
compatible = "qcom,ipcc";
reg = <0x0 0x00488000 0x0 0x1000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
num_mbox_chans = <5>;
};

sail_mailbox: sail-mailbox@1ffe02c {
compatible = "qcom,sail-mailbox";
reg = <0x0 0x01FFE02C 0x0 0x10>,
<0x0 0x01FFD018 0x0 0x10>,
<0x0 0x17C0000C 0x0 0x04>;
mboxes = <&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x2>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL1 0x3>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x4>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x5>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x6>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0x7>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL2 0x8>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL1 0x9>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL2 0xa>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL1 0xb>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0xc>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL0 0xd>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL1 0xe>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL2 0xf>,
<&ipcc_computeL1 IPCC_CLIENT_SAIL3 0x10>;
memory-region = <&sail_mailbox_mem>,
<&sail_ota_mem>;
interrupt-parent = <&ipcc_computeL1>;
interrupts = <IPCC_CLIENT_SAIL0 0x2 IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL1 0x3 IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL0 0x4 IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL0 0x5 IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL0 0x6 IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL0 0x7 IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL2 0x8 IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL1 0x9 IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL2 0xa IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL1 0xb IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL0 0xc IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL0 0xd IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL1 0xe IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL2 0xf IRQ_TYPE_EDGE_RISING>,
<IPCC_CLIENT_SAIL3 0x10 IRQ_TYPE_EDGE_RISING>;
sail-handshake-delay = <50000>;
status = "okay";
};
};
4 changes: 4 additions & 0 deletions include/dt-bindings/mailbox/qcom-ipcc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,10 @@
#define IPCC_CLIENT_NSP1 18
#define IPCC_CLIENT_TME 23
#define IPCC_CLIENT_WPSS 24
#define IPCC_CLIENT_SAIL0 27
#define IPCC_CLIENT_SAIL1 28
#define IPCC_CLIENT_SAIL2 29
#define IPCC_CLIENT_SAIL3 30
#define IPCC_CLIENT_GPDSP0 31
#define IPCC_CLIENT_GPDSP1 32

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