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Add a Verilator simulation flow for the mesh
gitlab-CI
#168:
Pull request
#98
synchronize by
FrancescoConti
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fc/verilator-squash
fc/verilator-squash
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Add a Verilator simulation flow for the mesh
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6h 0m 19s
fc/verilator-squash
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Add a Verilator simulation flow for the mesh
gitlab-CI
#166:
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2h 46m 3s
fc/verilator-squash
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Add a Verilator simulation flow for the mesh
gitlab-CI
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40m 37s
fc/verilator-squash
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Add a Verilator simulation flow for the mesh
gitlab-CI
#164:
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fc/verilator-squash
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Add a Verilator simulation flow for the mesh
gitlab-CI
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4h 10m 13s
fc/verilator-squash
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Removed RI5CY and re-enabled CV32E40X in memory-mapped mode
gitlab-CI
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lb/core-rework
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Removed RI5CY and re-enabled CV32E40X in memory-mapped mode
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Removed RI5CY and re-enabled CV32E40X in memory-mapped mode
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[HOTFIX] Update fractal_sync version to avoid race condition
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[HOTFIX] Update fractal_sync version to avoid race condition
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25s
fc/hotfix-fsync-race
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[HOTFIX] Update fractal_sync version to avoid race condition
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19m 25s
fc/hotfix-fsync-race
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Removed RI5CY and re-enabled CV32E40X in memory-mapped mode
gitlab-CI
#152:
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opened by
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6h 0m 19s
lb/core-rework
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Updated README
gitlab-CI
#151:
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Improvement of the RTL compilation and simulation flow
gitlab-CI
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18s
an/flow-improvement
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Improvement of the RTL compilation and simulation flow
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Improvement of the RTL compilation and simulation flow
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6m 31s
an/flow-improvement
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Improvement of the RTL compilation and simulation flow
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28m 29s
an/flow-improvement
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28m 29s
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Improvement of the RTL compilation and simulation flow
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AlessandroNadalini
4m 20s
an/flow-improvement
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4m 20s
View #86
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Improvement of the RTL compilation and simulation flow
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6h 0m 31s
an/flow-improvement
an/flow-improvement
6h 0m 31s
View #86
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Improvement of the RTL compilation and simulation flow
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6h 0m 19s
an/flow-improvement
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