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fix(personaplex): build the FP16 profile with a Half core - #1795
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The primary PersonaPlex profile declares FP16 but selected fp32_layers [0, 1], which promotes both autoregressive components (temporal and depth) to FP32 while its Native baseline runs the core in FP16. Clear the selector so the FP16 profile builds Half temporal and depth engines (Half hidden states and KV caches); Mimi keeps its FP32 encoder and decoder. Only the authoritative manifest field changes; the reference-only benchmark configuration carries no precision settings and is unchanged. Refs NVIDIA#1786 Signed-off-by: chaofengw <chaofengw@nvidia.com>
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This was referenced Oct 18, 2026
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Remove component-promotion selectors from the primary FP16 manifest. Preserve the declared BF16 E2E reference and all existing thresholds. Refs NVIDIA#1786 Refs NVIDIA#1795 Signed-off-by: chaofengw <chaofengw@nvidia.com>
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Remove component-promotion selectors from the primary FP16 manifest. Preserve the declared BF16 E2E reference and all existing thresholds. Refs NVIDIA#1786 Refs NVIDIA#1795 Signed-off-by: chaofengw <chaofengw@nvidia.com>
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* fix(personaplex): decode with the FP32 Mimi codec Build the Mimi decoder in FP32, matching the encoder and native codec for every language-model precision. Closes #1750 Signed-off-by: chaofengw <chaofengw@nvidia.com> * fix(personaplex): keep RMSNorm epsilon in FP32 Create RMSNorm epsilon in FP32 so the 1e-8 value survives Half network construction. Closes #1779 Refs #1780 Signed-off-by: chaofengw <chaofengw@nvidia.com> * fix(personaplex): preserve Half embedding additions Sum audio embeddings before text and round each addition to Half for Half temporal engines. Closes #1778 Refs #1781 Signed-off-by: chaofengw <chaofengw@nvidia.com> * fix(personaplex): round the FP16 depth input like the reference Round depth projection weights, inputs, projection output and token embedding additions at the reference Half boundaries. Closes #1788 Refs #1789 Signed-off-by: chaofengw <chaofengw@nvidia.com> * fix(personaplex): preserve reference RoPE precision Construct RoPE angles and rotation in FP32, then restore the input dtype across the family decoder variants. Closes #1790 Refs #1791 Signed-off-by: chaofengw <chaofengw@nvidia.com> * fix(personaplex): round the SwiGLU gate product once Evaluate SiLU and its gate product in FP32, casting the combined result to the projection dtype once. Closes #1793 Refs #1794 Signed-off-by: chaofengw <chaofengw@nvidia.com> * fix(personaplex): build the FP16 profile with a Half core Remove component-promotion selectors from the primary FP16 manifest. Preserve the declared BF16 E2E reference and all existing thresholds. Refs #1786 Refs #1795 Signed-off-by: chaofengw <chaofengw@nvidia.com> * fix(personaplex): preserve residual input rounding Preserve rounded branch outputs before residual addition across the family decoder variants. Closes #1796 Refs #1797 Signed-off-by: chaofengw <chaofengw@nvidia.com> * fix(personaplex): store RMSNorm weights in the model dtype Round RMSNorm scale weights to the model dtype before the FP32 normalization computation. Closes #1799 Refs #1800 Signed-off-by: chaofengw <chaofengw@nvidia.com> --------- Signed-off-by: chaofengw <chaofengw@nvidia.com>
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Background
Refs #1786. The primary PersonaPlex profile declares
precision: fp16but selectsfp32_layers: [0, 1]. Thoseselectors promote both autoregressive components, the temporal transformer (selector 0) and the depth transformer
(selector 1), to FP32, while the formal AIPerf benchmark's Native baseline runs that core in FP16. (The manifest's E2E testcase
reference_precisionisbf16and is unchanged.) The requested product configuration isa true FP16 core: Half temporal and depth weights, hidden states and KV caches, with the Mimi codec in FP32 as before.
Exit Criteria
families/personaplex/tests/manifests/personaplex-7b.jsonresolves to an FP16 build withno FP32 component selectors.
reference_precisionor Native baseline.apps/aiperf_qual/config/models/personaplex-7b.yaml, which holds no precisionsettings, unchanged.
Implementation
fp32_layers: [0, 1]becomesfp32_layers: []in the authoritative manifest. No code changes.Change categories
Validation
Commands and Results
main9a8b545 and of this change resolvedpersonaplex-7bthroughtrtmc_benchmark.catalog.ManifestCatalogand generated the build command withtrtmc_benchmark.builder._build_command.main: precisionfp16,fp32_layers [0, 1], command arguments--fp32-layer 0 --fp32-layer 1.fp16,fp32_layers [], no--fp32-layerarguments.fp32_layers []) ondevelopment trees that also carried pending accuracy changes. The serialized plans were inspected directly.
engine.planand all 16depth.N.planengines usecache_k_0HALF.Hardware, Environment, and Revisions
GB300 (SBSA), CUDA 13.0, TensorRT 11.2.0.113. Checkpoint
nvidia/personaplex-7b-v1revisionfdaf4090a61cb315c138a1faee287ffd6c716309. Tested head05b41f087ad7a41f00e4b21494428468af1007fd.Not Run / Remaining Gaps
Native FP16 baseline (5.58 dB under the unchanged 3 dB gate). This holds even with the pending component fixes fix(personaplex): round the FP16 depth input like the reference #1789,
fix(personaplex): preserve reference RoPE precision #1791 and fix(personaplex): round the SwiGLU gate product once #1794 and the FP32 RMSNorm epsilon applied. The remaining temporal-path differences are under investigation.
that reference policy is a pending maintainer decision, and this PR does not change it.
yet for this head.
Contributor Self-Review
Notes For Future Readers
The FP16 profile now requests none of them.
Risk level
Medium: the default FP16 PersonaPlex build changes from an FP32 core to a Half core, which is the requested precision but
not yet audio-parity qualified.