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fix(personaplex): build the FP16 profile with a Half core - #1795

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chaofengw-nv:fix/personaplex-true-half-core-20261018

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@chaofengw-nv chaofengw-nv commented Oct 18, 2026 •

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Background

Refs #1786. The primary PersonaPlex profile declares precision: fp16 but selects fp32_layers: [0, 1]. Those
selectors promote both autoregressive components, the temporal transformer (selector 0) and the depth transformer
(selector 1), to FP32, while the formal AIPerf benchmark's Native baseline runs that core in FP16. (The manifest's E2E testcase
reference_precision is bf16 and is unchanged.) The requested product configuration is
a true FP16 core: Half temporal and depth weights, hidden states and KV caches, with the Mimi codec in FP32 as before.

Exit Criteria

  • The authoritative manifest families/personaplex/tests/manifests/personaplex-7b.json resolves to an FP16 build with
    no FP32 component selectors.
  • The resulting bundle's temporal and depth engines use Half KV caches.
  • Non-goals:
    • This PR does not claim the model passes the audio-parity benchmark.
    • It changes no gate, threshold, reference_precision or Native baseline.
    • It leaves the reference-only apps/aiperf_qual/config/models/personaplex-7b.yaml, which holds no precision
      settings, unchanged.

Implementation

  • fp32_layers: [0, 1] becomes fp32_layers: [] in the authoritative manifest. No code changes.

Change categories

  • Model or runtime behavior
  • Public API
  • ABI
  • Bundle or artifact format
  • Dependencies
  • Documentation only
  • CI or developer tooling

Validation

Commands and Results

  • Catalog resolution (CPU only, CUDA hidden): isolated trees of main 9a8b545 and of this change resolved
    personaplex-7b through trtmc_benchmark.catalog.ManifestCatalog and generated the build command with
    trtmc_benchmark.builder._build_command.
    • main: precision fp16, fp32_layers [0, 1], command arguments --fp32-layer 0 --fp32-layer 1.
    • This change: precision fp16, fp32_layers [], no --fp32-layer arguments.
  • Engine dtypes on GB300 (diagnostic builds, not this head): bundles built with the same request (fp32_layers []) on
    development trees that also carried pending accuracy changes. The serialized plans were inspected directly.
    • The temporal engine.plan and all 16 depth.N.plan engines use cache_k_0 HALF.
    • The Mimi encoder and decoder plans are FP32.

Hardware, Environment, and Revisions

GB300 (SBSA), CUDA 13.0, TensorRT 11.2.0.113. Checkpoint nvidia/personaplex-7b-v1 revision
fdaf4090a61cb315c138a1faee287ffd6c716309. Tested head 05b41f087ad7a41f00e4b21494428468af1007fd.

Not Run / Remaining Gaps

Contributor Self-Review

  • I have completed a self-review of this change.

Notes For Future Readers

  • Selector meaning in this family: 0 = temporal, 1 = depth, 2 and 3 = Mimi components, 4 and above = temporal blocks.
    The FP16 profile now requests none of them.
  • Bundles built from the earlier profile have FP32 temporal and depth engines and should be rebuilt.

Risk level

  • Low
  • Medium
  • High

Medium: the default FP16 PersonaPlex build changes from an FP32 core to a Half core, which is the requested precision but
not yet audio-parity qualified.

The primary PersonaPlex profile declares FP16 but selected fp32_layers [0, 1],
which promotes both autoregressive components (temporal and depth) to FP32
while its Native baseline runs the core in FP16. Clear the selector so the
FP16 profile builds Half temporal and depth engines (Half hidden states and
KV caches); Mimi keeps its FP32 encoder and decoder.

Only the authoritative manifest field changes; the reference-only benchmark
configuration carries no precision settings and is unchanged.

Refs NVIDIA#1786

Signed-off-by: chaofengw <chaofengw@nvidia.com>
@chaofengw-nv chaofengw-nv self-assigned this Oct 18, 2026
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chaofengw-nv added a commit to chaofengw-nv/TensorRT-Model-Connect-fork that referenced this pull request Oct 20, 2026
Remove component-promotion selectors from the primary FP16 manifest. Preserve the declared BF16 E2E reference and all existing thresholds.

Refs NVIDIA#1786
Refs NVIDIA#1795

Signed-off-by: chaofengw <chaofengw@nvidia.com>
@chaofengw-nv

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Superseded by #1751. This change and its regression coverage are preserved in commit 40288a4 of the consolidated PR. Original issue links and acceptance criteria remain tracked there.

chaofengw-nv added a commit to chaofengw-nv/TensorRT-Model-Connect-fork that referenced this pull request Oct 21, 2026
Remove component-promotion selectors from the primary FP16 manifest. Preserve the declared BF16 E2E reference and all existing thresholds.

Refs NVIDIA#1786
Refs NVIDIA#1795

Signed-off-by: chaofengw <chaofengw@nvidia.com>
chaofengw-nv added a commit that referenced this pull request Oct 21, 2026
* fix(personaplex): decode with the FP32 Mimi codec

Build the Mimi decoder in FP32, matching the encoder and native codec for every language-model precision.

Closes #1750

Signed-off-by: chaofengw <chaofengw@nvidia.com>

* fix(personaplex): keep RMSNorm epsilon in FP32

Create RMSNorm epsilon in FP32 so the 1e-8 value survives Half network construction.

Closes #1779
Refs #1780

Signed-off-by: chaofengw <chaofengw@nvidia.com>

* fix(personaplex): preserve Half embedding additions

Sum audio embeddings before text and round each addition to Half for Half temporal engines.

Closes #1778
Refs #1781

Signed-off-by: chaofengw <chaofengw@nvidia.com>

* fix(personaplex): round the FP16 depth input like the reference

Round depth projection weights, inputs, projection output and token embedding additions at the reference Half boundaries.

Closes #1788
Refs #1789

Signed-off-by: chaofengw <chaofengw@nvidia.com>

* fix(personaplex): preserve reference RoPE precision

Construct RoPE angles and rotation in FP32, then restore the input dtype across the family decoder variants.

Closes #1790
Refs #1791

Signed-off-by: chaofengw <chaofengw@nvidia.com>

* fix(personaplex): round the SwiGLU gate product once

Evaluate SiLU and its gate product in FP32, casting the combined result to the projection dtype once.

Closes #1793
Refs #1794

Signed-off-by: chaofengw <chaofengw@nvidia.com>

* fix(personaplex): build the FP16 profile with a Half core

Remove component-promotion selectors from the primary FP16 manifest. Preserve the declared BF16 E2E reference and all existing thresholds.

Refs #1786
Refs #1795

Signed-off-by: chaofengw <chaofengw@nvidia.com>

* fix(personaplex): preserve residual input rounding

Preserve rounded branch outputs before residual addition across the family decoder variants.

Closes #1796
Refs #1797

Signed-off-by: chaofengw <chaofengw@nvidia.com>

* fix(personaplex): store RMSNorm weights in the model dtype

Round RMSNorm scale weights to the model dtype before the FP32 normalization computation.

Closes #1799
Refs #1800

Signed-off-by: chaofengw <chaofengw@nvidia.com>

---------

Signed-off-by: chaofengw <chaofengw@nvidia.com>
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