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MT-151599: arm64: dts: mt-connect: fix SAI MCLK direction, add SAI2/SAI3 pinctrl, fix SAI2 dataline #44

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MT-151599: arm64: dts: mt-connect: fix SAI MCLK direction, add SAI2/SAI3 pinctrl, fix SAI2 dataline #44

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f3f375d
arm64: dts: mt-connect: fix SAI MCLK direction and add SAI2/SAI3 MCLK…
AmeNote-Michael Jul 8, 2026
c3540d2
arm64: dts: mt-connect: add fsl,dataline to sai2 to fix probe crash
AmeNote-Michael Jul 9, 2026
f0b6626
Potential fix for pull request finding
AmeNote-Michael Jul 9, 2026
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35 changes: 25 additions & 10 deletions arch/arm64/boot/dts/freescale/mt-connect.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -439,8 +439,6 @@
};

&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5>;
gpio-line-names = "DPM_HP_DAC_BCLK", "DPM_HP_DAC_SD", "DPM_HP_DAC_MCLK", "", "", "PWM_MEMBRANE", "", "",
"", "", "SPI2_SCK", "SPI2_MOSI", "SPI2_MISO", "SPI2_NSS", "", "",
"DPM_I2C2_SCL", "DPM_I2C2_SDA", "", "", "DPM_I2C4_SCL", "DPM_I2C4_SDA", "", "",
Expand All @@ -466,7 +464,6 @@
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
fsl,dataline = <1 0x00 0x01>; /*I2S mode enabled, 0 RX lines, 1 TX lines*/
fsl,txs-rxs;
fsl,sai-mclk-direction-output;
status = "okay";
};

Expand All @@ -480,7 +477,24 @@
fsl,dataline = <1 0x0F 0x0F>; /*I2S mode enabled, 4 RX lines, 4 TX lines*/
fsl,txs-rxs;
fsl,sai-multi-lane;
fsl,sai-mclk-direction-output;
status = "okay";
};

/*
* SAI2 TXFS/TXC share the Dante clock bus with SAI1 and SAI3; no data lines
* are used. fsl,dataline must be present even with zero lanes -- without it
* fsl_sai_read_dlcfg calls devm_kzalloc(0) which returns ZERO_SIZE_PTR and
* immediately crashes on the first cfg[0] write.
*/
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>,
<&dante_osc_mclk>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
fsl,dataline = <1 0x00 0x00>; /* no RX or TX data lines */
fsl,txs-rxs;
status = "okay";
};

Expand Down Expand Up @@ -688,12 +702,19 @@
>;
};

pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x80 /* Dante LRCLK shared bus */
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x80 /* Dante BCLK shared bus */
>;
};

pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x80 /* DANTE_OSC_SCLK */
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 /* DPM_HP_DAC_SD */
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x80 /* DPM_HP_DAC_LRCK */
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x80 /* DANTE_OSC_MCLK input */
>;
};

Expand All @@ -704,12 +725,6 @@
>;
};

pinctrl_gpio5: gpio5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x80 /* DANTE_OSC_MCLK */
>;
};

pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
Expand Down