MT-151599: arm64: dts: mt-connect: fix SAI MCLK direction, add SAI2/SAI3 pinctrl, fix SAI2 dataline

[AmeNote-Michael]

Summary

• Remove fsl,sai-mclk-direction-output from SAI1 and SAI3. All MCLK signals are generated by the Dante Clocking Circuit (SI5351B) and flow into the A53 — none are SoC outputs. For SAI1 the MCLK pad (AB18) is NC so this was harmless; for SAI3 (AD6) the output driver was contending with the SI5351B CLK2 output.
• Move SAI3_MCLK (AD6) from pinctrl_gpio5 to pinctrl_sai3 using ALT0 (SAI3_MCLK function) so the 24.576 MHz Dante MCLK is properly routed into the SAI3 peripheral.
• Add pinctrl_sai2 and enable &sai2 (no sound card, no data lines) to claim SAI2_TXFS (AD23) and SAI2_TXC (AD22) as inputs. These pads share the Dante BCLK/LRCLK bus with SAI1 and SAI3.
• Add fsl,dataline = <1 0x00 0x00> to SAI2. Without this, fsl_sai_read_dlcfg computes num_cfg=0, calls devm_kzalloc(0) which returns ZERO_SIZE_PTR (0x10), and immediately faults on the first cfg[0] write.
• Remove now-empty pinctrl_gpio5 group and its reference from &gpio5.

Test plan

• Verified on MT Connect (iMX8MM) running kernel 6.6.36, device at 10.0.0.51
• fsl,sai-mclk-direction-output absent from SAI1 and SAI3 DT nodes
• SAI2 fsl,dataline = <1 0x00 0x00> present in running DT
• SAI3_MCLK (pin 121) in sai3grp with config 0x80 (was in gpio5grp)
• SAI2_TXFS/SAI2_TXC (pins 111/112) in sai2grp with config 0x80
• gpio5grp absent from pinctrl-handles
• SAI2 bound to fsl-sai driver with no probe crash

AI Generation Record

Tool: Claude Sonnet 4.6 (Claude Code)
Scope: Plan started with validating current "final" state of MT Connect to confirm that the hardware register settings were correct against reference manual. The above issues were realized - therefore plan extended to update the current linux-imx to implement changes. Extensive testing to validate functionality occurred. Oscilloscope used to validate signal integrity.
Security review: No credentials/keys/secrets; no GPL code; no shell injection vectors
Code review: Full local agent review.

DevQA: @dnappier-mt

[Copilot]

Pull request overview

This PR updates the MT Connect (iMX8MM) device tree to correctly model SAI clock/pin direction for a design where Dante-generated MCLK/BCLK/LRCLK are inputs to the SoC, and to prevent an SAI2 probe crash by ensuring fsl,dataline is present.

Changes:

• Remove fsl,sai-mclk-direction-output from &sai1 and &sai3.
• Add and enable an &sai2 node with pinctrl_sai2 and a zero-lane fsl,dataline configuration.
• Move SAI3 MCLK muxing into pinctrl_sai3 and remove the now-unused pinctrl_gpio5 group (and the &gpio5 pinctrl reference).

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[Copilot]

Pull request overview

Copilot reviewed 1 out of 1 changed files in this pull request and generated no new comments.

[AmeNote-Michael]

Main thing to note that this resolves is the MCLK being overdriven excessively. Still not positive why we have a 4.56V signal on MCLK, but better than 6.4V. Forgot to get a zoom in of MCLK, but the signal quality is also much better now that only a single line driver. This signal line quality also propogates into BCLK - not so much LRCLK.

Here is original statistical trace from current 0.1.2 release candidate:

Here is new statistical trace from this modification to device tree:

Note that UBOOT still has old settings which therefore will overdrive clock lines briefly. Probabaly should propogate changes to UBOOT. But as audio does not really start until after Linux fully up, not necessarily an operational issue, however do not like overdriving lines of connected devices. The STM32 connection should be good, the iMX is hairy edge, the HP DAC we are exceeding by a fair bit.