Add PIC32MZ EF bare-metal wolfIP port: clocks, UART2, wolfCrypt RNG, LAN8740 PHY#140
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Add PIC32MZ EF bare-metal wolfIP port: clocks, UART2, wolfCrypt RNG, LAN8740 PHY#140dgarske wants to merge 1 commit into
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Pull request overview
Adds a new bare-metal PIC32MZ EF architecture port under src/port/pic32mz/, providing early bring-up infrastructure (clocks, UART console, timebase), a wolfCrypt hardware TRNG self-test configuration, and initial Ethernet EMAC MDIO + LAN8740 PHY link bring-up scaffolding.
Changes:
- Introduces PIC32MZ EF device configuration and 200 MHz clock/flash setup, plus a CP0-based millisecond timebase.
- Adds UART2 console support with XC32
printfretargeting and a standalone wolfCrypt RNG self-test usingWOLFSSL_PIC32MZ_RNG. - Adds initial EMAC MII-management (MDIO) routines and a MAC-agnostic LAN8740 PHY bring-up module, with a command-line XC32 Makefile build/flash flow.
Reviewed changes
Copilot reviewed 20 out of 20 changed files in this pull request and generated 4 comments.
Show a summary per file
| File | Description |
|---|---|
| src/port/pic32mz/.gitignore | Ignores XC32/MDB build and flash artifacts for the new port. |
| src/port/pic32mz/Makefile | XC32-based command-line build/flash rules and wolfCrypt source inclusion for self-test. |
| src/port/pic32mz/board.h | Board- and clock-related constants (SYSCLK/PBCLK, UART pins, LEDs). |
| src/port/pic32mz/cache.h | MIPS KSEG address helpers intended for coherent DMA/EMAC access patterns. |
| src/port/pic32mz/clock_init.c | Flash wait-state and prefetch configuration for 200 MHz operation. |
| src/port/pic32mz/clock_init.h | Declares clock/flash init routine for the port. |
| src/port/pic32mz/device_config.c | PIC32MZ DEVCFG0-3 configuration word settings for the target board. |
| src/port/pic32mz/main.c | Bring-up application tying together clock, UART, timebase, RNG self-test, and PHY init. |
| src/port/pic32mz/phy_lan8740.c | LAN8740 PHY scanning/reset/autoneg/link reporting via MDIO function pointers. |
| src/port/pic32mz/phy_lan8740.h | PHY driver API and link-status struct definitions. |
| src/port/pic32mz/pic32mz_eth.c | EMAC module enable/reset and clause-22 MDIO read/write primitives. |
| src/port/pic32mz/pic32mz_eth.h | EMAC/MDIO init and accessor function declarations. |
| src/port/pic32mz/rng_selftest.c | Standalone RNG self-test using wolfCrypt WC_RNG + coarse sanity checks. |
| src/port/pic32mz/rng_selftest.h | Declares the RNG self-test entrypoint. |
| src/port/pic32mz/timebase.c | CP0 Count-derived 64-bit extended counter and millis()/delay_ms(). |
| src/port/pic32mz/timebase.h | Declares millis()/delay_ms() timebase API. |
| src/port/pic32mz/uart_console.c | UART2 init, TX/RX helpers, and XC32 _mon_putc retarget. |
| src/port/pic32mz/uart_console.h | UART console API declarations and usage notes. |
| src/port/pic32mz/user_settings.h | wolfCrypt feature selection for PIC32MZ RNG self-test (trimmed algorithms, no FS/sockets). |
| src/port/pic32mz/wolf_compat.c | wolfCrypt min/max shim functions for the bare-metal environment. |
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| ROOT := ../../.. | ||
| WOLFSSL_ROOT ?= /home/davidgarske/GitHub/wolfssl | ||
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| CFLAGS_WC := -mprocessor=$(DEVICE) -mdfp="$(DFP)" -O1 -g \ | ||
| -ffunction-sections -fdata-sections \ | ||
| -DWOLFSSL_USER_SETTINGS -I. -I$(WOLFSSL_ROOT) -w |
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| else | ||
| printf("[PHY] no PHY found on MDIO bus (ID=0xFFFF)\r\n"); |
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| ETH_TRACE("a: ETHCON1 off"); | ||
| ETHCON1CLR = _ETHCON1_ON_MASK; | ||
| timeout = MII_TIMEOUT; | ||
| while ((ETHSTAT & _ETHSTAT_ETHBUSY_MASK) && (timeout != 0)) | ||
| timeout--; | ||
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Add PIC32MZ EF bare-metal wolfIP port
New bare-metal wolfIP port for the Microchip PIC32MZ EF Starter Kit (PIC32MZ2048EFM144, MIPS32 M-class) with a LAN8740 PHY daughter board over RMII. This is a brand-new architecture for wolfIP (first MIPS/PIC32 target) and also verifies wolfCrypt's built-in hardware TRNG (
WOLFSSL_PIC32MZ_RNG). Early bring-up code is factored so a future wolfBoot PIC32MZ port can reuse it. All new code lives undersrc/port/pic32mz/.Features
make,xc32-gcc), matching the other wolfIP ports; no MPLAB X project required. Targets32MZ2048EFM144via the PIC32MZ-EF DFP,-O1(free XC32 tier).device_config.c,clock_init.c): DEVCFG0-3 config words (POSC EC 24 MHz -> SPLL 200 MHz SYSCLK, PBCLK2/PBCLK5 = 100 MHz, RMII selected), flash wait-states and prefetch. Isolated for wolfBoot reuse.uart_console.c): 115200 8N1 on RPB14 (U2TX) / RPG6 (U2RX) with PPS mapping, plus XC32_mon_putcretarget soprintfgoes to the serial console.timebase.c): 64-bitmillis()derived from the CP0 core-timer with software wrap extension; drives the wolfIP poll loop.rng_selftest.c,user_settings.h): exercisesWOLFSSL_PIC32MZ_RNG, generating and sanity-checking random blocks. Compiles the needed wolfcrypt sources directly from the sibling wolfssl checkout; keeps the crypto engine hash/AES acceleration off so SHA-256 (DRBG) stays software for this milestone.pic32mz_eth.c): EMAC + RMII + MII-management bring-up, clause-22 MDIO read/write primitives, and PBCLK5 / PMD6 module enable before EMAC access.phy_lan8740.c): MAC-agnostic (function-pointer MDIO), scans for the PHY, resets, advertises 10/100 full/half, runs auto-negotiation, and reports resolved link speed/duplex.cache.h): KSEG0/KSEG1 and virtual/physical macros for coherent EMAC descriptor/buffer access.make flash): uses MPLAB X v6.20 MDB (the on-board Starter Kit debugger was dropped in v6.30; headlessipecmdcannot resolve device packs, MDB can), with erase-before-program.Hardware verification status
RNG self-test: PASS, distinct entropy each boot).Scope
Milestone 1: network stack bring-up path plus the RNG self-test. Full EMAC RX/TX DMA rings, DHCP, and a TCP echo/speed-test app are the next phase and are not included here.