Enable flash

[jinwjinl]

Enable to read and write nor-flash. It has been verified by connecting W25Q64 in ESP32C3. Note:
CS : GPIO5,
DI : GPIO9,
DO : GPIO10,
CLK : GPIO8.

[jinwjinl]

build_prs #434 vivoblueos/external#27

[github-actions]

Job is started, see https://github.com/vivoblueos/kernel/actions/runs/28585965485.

[github-actions]

❌ Job failed. Failed jobs: build_and_check_boards (failure), see https://github.com/vivoblueos/kernel/actions/runs/28585965485.

[jinwjinl]

build_prs #434 vivoblueos/external#27

[github-actions]

Job is started, see https://github.com/vivoblueos/kernel/actions/runs/28586350982.

[github-actions]

✅ All jobs completed successfully, see https://github.com/vivoblueos/kernel/actions/runs/28586350982.

[han-jiang277]

1. spi_flash.rs:162 — Silent partial read on erase-block boundary
   read_blocks returns Ok(()) after copying only the in-cache portion of a multi-sector buffer that crosses an erase-block boundary. Block::read passes the full multi-sector buffer in one call, so any read spanning two erase blocks while the first is dirty delivers truncated data with no error signal.
2. esp32_gpio.rs:68 — GPIO 1 << PIN overflows for PIN ≥ 26
   GpioOut::DATA is 26 bits wide. For PIN in [26, 31] the bit is masked to 0 — the pin is never driven. For PIN ≥ 32Rust panics (debug) or wraps to pin PIN % 32 (release). No compile-time bound exists.

[xuchang-vivo]

We need to confirm whether these commands are specific to the W25Q80 or are generic (common to other flash chips).

[jinwjinl]

These command codes are JEDEC 25-series SPI NOR Flash standard commands, not specific to the W25Q80. The file header is marked with //! JEDEC 25-series SPI NOR Flash command layer., consistent with the Winbond W25Q80 datasheet, and also applicable to chips conforming to the same standard, such as W25Q64 / W25Q128.

Refer to the Linux kernel include/linux/mtd/spi-nor.h: https://raw.githubusercontent.com/torvalds/linux/master/include/linux/mtd/spi-nor.h