Add AM62L LPDDR4 two-bus fanout repro

[seveibar]

Summary

• add a self-contained PCB snapshot repro using the real 373-ball AM62L32 and 200-ball MT53E1G16D1ZW LPDDR4 footprint geometry
• route two complete DDR byte buses—BYTE0 DQ0-DQ7 and BYTE1 DQ8-DQ15—through independent AM62L and DRAM fanout breakouts
• use autorouter="fanout" for both package phases and autorouter="default" for the single parent-board global phase
• route BYTE0 on top/inner1 and BYTE1 on inner2/bottom of a compact four-layer board, with package-appropriate top exits from the AM62L and left exits from the rotated DRAM
• use an explicit 300-second allowance for this dense 16-signal routing repro
• assert the routing phase inputs are [16, 16, 16]: AM62L fanout, DRAM fanout, then global routing
• assert the two fanouts preload 32 traces and the completed three-stage route emits 48 PCB trace records without autorouting errors

The PCB snapshot labels phase 0 around the AM62L fanout, phase 1 around the DRAM fanout, and phase 2 around the global route so the solver hierarchy is directly visible.

Source

Adapted from https://tscircuit.com/0hmX/am62l-lpddr4-ti-pth-router#files

This is intentionally a routing-quality reproduction, not a production DDR design. It omits power, ground, decoupling, impedance, timing, and length-matching constraints.

Validation

• bun test tests/repros/repro-am62l-lpddr4-two-bus-fanout.test.tsx
• bunx tsc --noEmit
• git diff --check

Stacking

Merge this baseline first. Core #3382 is based on this branch so its PCB snapshot comparison directly records whether the winding-destination change affects either fanout.

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Project	Deployment	Actions	Updated (UTC)
tscircuit-core-benchmarks	Ready	Preview	Aug 23, 2026 5:07pm

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PR Rating: ⭐⭐
Impact: Minor

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