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uart-apb-interfacing

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RamnarayanBalai / UART-Design-Verification

A synthesizable UART design with an AMBA APB3 slave interface. Verified using SystemVerilog, Assertions (SVA), and functional coverage.

coverage assertions uart systemverilog sva apb functional-verification amba-apb functional-coverage systemverilog-assertions apb-protocol uart-apb-interfacing

Updated Jun 20, 2026
SystemVerilog

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