Opensource DDR3 Controller
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Sep 12, 2026 - Verilog
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memory-controller
Here are 39 public repositories matching this topic...
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
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Dec 1, 2022 - Verilog
mirror of https://git.elphel.com/Elphel/eddr3
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Oct 16, 2017 - Verilog
UEFI memory diagnostic tool - 14 stress tests, per-chip stuck-bit mapping, MCA capture, marathon mode, plain-language verdict with DIMM warranty info
c hardware uefi diagnostics memtest low-level dram efi gnu-efi spd ddr3 memory-controller ddr4 ddr5 memory-testing
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May 31, 2026 - C
This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).
linux arm kernel linux-kernel tesla armv7 samsung odroid arm64 devicetree snapdragon qualcomm armv8 exynos fsd qcom memory-controller samsung-soc gs101 gs201
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Sep 16, 2026 - C
Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench
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Aug 15, 2026 - Verilog
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
memory verilog sram memory-management vivado questasim sdram sdram-controller memory-controller verilog-project vlsi-design sram-controller sram-controller-advanced sram-features-power-security-brust verlog-hdl enhanched-sram-controller
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Oct 21, 2024 - Verilog
A bare-metal SRAM memory controller suitable for Xilinx FPGAs.
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Jan 15, 2024 - Verilog
A flexible memory control framework to reduce the repeated DRAM interface and controller modifications required by DRAM techniques via custom DRAM command extensions and a programmable memory controller, as described in the MICRO 2026 paper by Songara et al.
interface latency parallelism maintenance dram flexibility memory-controller rowhammer processing-using-dram
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Sep 29, 2026 - C++
SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.
python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project
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May 14, 2026 - SystemVerilog
🛠 A SDRAM controller in Verilog HDL
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Mar 21, 2022 - Verilog
This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.
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Feb 16, 2026 - SystemVerilog
Industrial asynchronous dual-port RAM subsystem in Verilog with CDC synchronizers and AXI-style handshake interface.
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Oct 3, 2026 - Verilog
This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.
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Feb 15, 2026 - Verilog
HBM4 System Modeling Platform - High Bandwidth Memory simulation and verification framework
python dram uvm system-verilog hbm semiconductor memory-controller chip-design high-bandwidth-memory hbm4
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Jul 8, 2026 - Python
DDR memory controller implementation and verification
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Oct 6, 2025
Behavioral architecture of a read/write cycle controller for a DRAM chip.
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May 26, 2023 - VHDL
132 protocol entries: 110 UVM VIPs + 22 RTL IP companions (AMBA/DDR/PCIe/CXL/USB/MIPI...) — L1-L4 SVA, smoke-verified, pyslang/iverilog/verilator gates. Apache-2.0.
coverage asic fpga verification vip riscv systemverilog uvm formal-verification testbench pcie amba memory-controller hardware-verification chip-design
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Oct 3, 2026 - Python
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