fault-coverage

Here are 4 public repositories matching this topic...

HugoHuang-dev / rtl-mbist-fault-coverage

March C− RTL MBIST with automated fault coverage evaluation, Artix-7 FPGA validation, and Nangate45 ASIC synthesis and timing analysis.

asic fpga rtl verilog systemverilog yosys static-timing-analysis design-verification openroad artix-7 mbist march-algorithm fault-coverage

Updated Oct 2, 2026
Python

kevin9327 / hbmlens

Star

Read HBM failures like an inspection image: memory test patterns on a virtual HBM and real GPUs (CUDA), measured fault coverage, fail-signature analysis and a 3D viewer.

threejs gpu cuda dram hbm failure-analysis memory-testing fault-coverage march-test

Updated Sep 28, 2026
Python

SriKondapaturi / fsm-traffic-bist-atpg

Star

Design, verification, synthesis, and ATPG analysis of a Verilog FSM traffic controller with BIST. 90.93% fault coverage, 144.7 µm² area, 68.6 µW total power. Built with Synopsys DC + TetraMAX on the Nangate 45nm Open Cell Library.

dft verilog synthesis atpg bist scan-chain fault-coverage tetramax

Updated May 22, 2026
Verilog

SandeepGorrepati / dft-scan-atpg

Star

Full-scan insertion + a from-scratch stuck-at ATPG and fault simulator. 100% testable fault coverage, 9 patterns, 0 redundant. Verilog + Python, runs on Icarus.

python dft verification scan verilog vlsi atpg fault-coverage

Updated Jun 26, 2026
Python

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