Parallel FPGA architecture for prime number discovery based on the Cyclic Prime Emergence Algorithm, featuring O(1) per-step primality check without memory.
cryptography fpga vhdl parallel-computing prime-numbers digital-logic hardware-acceleration number-theory zenodo open-source-hardware hardware-description-language prime-search hardware-design algorithmic-efficiency cycles-deterministic
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Updated
Jun 15, 2026 - VHDL