This repo contains the verification basics of System verilog and UVM
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Sep 3, 2025 - SystemVerilog
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class-based-verification
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Phase-2 Cycle-3: Verification Fundamentals
randomization assertions constrained-random-verification functional-coverage class-based-verification cross-coverage self-checking-testbench
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Aug 30, 2026 - SystemVerilog
RTL implementation and class-based verification of a Direct-Mapped Cache Controller using SystemVerilog with a self-checking scoreboard, directed and constrained-random testing.
verification systemverilog computer-architecture vlsi testbench digital-design cache-controller rtl-design-and-verification class-based-verification
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Jul 28, 2026 - SystemVerilog
Asynchronous FIFO verification using both traditional Verilog testbenches and a full Python Cocotb environment. Includes CDC-focused FIFO design analysis, dual-clock stimulus, waveform debugging with GTKWave, and validation on QuestaSim and Icarus Verilog.
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Nov 16, 2025 - Python
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