bcm2835-i2s: fail capture open cleanly when FIFO clear has no clock - #7586
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pelwell merged 1 commit intoSep 1, 2026
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Replace this FIXME with a one-line explanation of the slave mode problem, e.g.
The reset will timeout in clock consumer mode without an external clock.
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This PR is more readable than the associated issue (#7585), and would have been sufficient on its own. Apart from my comment about the FIXME and the commit title (drop the |
In clock-consumer (slave) mode the RX/TX FIFO clear requires PCM clock cycles to complete. When the external bit clock is absent at open time (source device off or unplugged), the SYNC round trip times out, the FIFOs are left uncleared, and starting DMA on top of the stale RX FIFO makes capture free-run: DREQ sticks high, the same dead word is re-read at bus speed, and the poisoned state survives further stream cycles until reboot. Return an error from bcm2835_i2s_clear_fifos() on SYNC timeout and propagate it in .prepare for the capture branch that clears stale RX data, so the open fails with -EIO instead of recording garbage. The hw_params-time clear stays tolerant: on clock-consumer links it runs legitimately before the provider's clocks are up, and the .prepare clear is the one that must succeed there. Validated on a Raspberry Pi 4B (6.18.34+rpt-rpi-v8) with a WM8804 S/PDIF receiver board as clock provider: opening capture with the optical source unplugged now fails cleanly in ~0.6s with no bogus data, and the next open after the source returns captures normally, with no reboot needed. Fixes: c6aeb7d ("ASoC: Add support for BCM2835") Signed-off-by: Guilherme Silva Sousa <guisousa09@hotmail.com>
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Thanks for the review! All three points addressed in the updated commit:
Re-tested on the same Pi 4B rig after the amend: unplugged-source capture opens still fail cleanly with -EIO and recovery on reconnect remains immediate. |
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Thanks! |
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Fixes #7585
In clock-consumer (slave) mode the RX/TX FIFO clear requires PCM clock cycles to complete. When the external bit clock is absent at open time (source off/unplugged), the SYNC round trip times out, the FIFOs are left uncleared, and starting DMA on top of the stale RX FIFO makes capture free-run: DREQ sticks high, the same dead word is re-read at bus speed, and the poisoned state survives further stream cycles until reboot.
This change makes
bcm2835_i2s_clear_fifos()return an error on SYNC timeout and propagates it in.preparefor the capture branch that clears stale RX data, so the open fails with-EIOinstead of recording garbage. Thehw_params-time clear stays tolerant on purpose: on clock-consumer links it legitimately runs before the provider's clocks are up, and the.prepareclear is the one that must succeed there.Tested on: Raspberry Pi 4B, 6.18.34+rpt-rpi-v8, HiFiBerry Digi+ I/O (WM8804 as clock provider,
dtoverlay=hifiberry-digi):-EIOin ~0.6 s, zero bogus data (previously: instant "success" full of DC garbage + FIFO poisoned until reboot);