[qcom-next] serial: msm_geni: validate RX data with IRQ status - #88
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[qcom-next] serial: msm_geni: validate RX data with IRQ status#88balajiselvanathan wants to merge 131 commits into
balajiselvanathan wants to merge 131 commits into
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Add clock support for SDCC1 (eMMC) and SDCC2 (SD card) controllers on QCS615 platform. This enables proper clock configuration for both storage interfaces. Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
The block device removable flag should reflect whether the MMC device is physically removable (SD card) or soldered (eMMC). This information is specified in the device tree via the "non-removable" property and stored in the MMC_CAP_NONREMOVABLE capability flag. Update the removable flag in the block device descriptor during controller probe to properly reflect the device's removable status. This allows the block layer and upper layers (particularly EFI boot manager) to distinguish between eMMC and SD cards for appropriate handling. The default removable=1 is set in mmc_bind(), and this change overrides it only for non-removable devices after mmc_of_parse() has set the MMC_CAP_NONREMOVABLE capability from the device tree. Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
…r timeout Set CONFIG_SYS_MMC_MAX_BLK_COUNT to 16384 blocks to limit the maximum transfer size per operation. This prevents controller timeouts. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
NVMEM cells currently only support byte-level access. Many hardware
registers pack multiple fields into single bytes, requiring bit-level
granularity. For example, Qualcomm PMIC PON registers store a 7-bit
reboot reason field within a single byte, with bit 0 reserved for other
purposes.
Add support for the optional 'bits' property in NVMEM cell device tree
bindings. This property specifies <bit_offset num_bits> to define a bit
field within the cell's register space.
Implement bit‑field handling in the driver to max u32 size
Example device tree usage:
reboot-reason@48 {
reg = <0x48 0x01>;
bits = <0x01 0x07>; /* 7 bits starting at bit 1 */
};
This reads bits [7:1] from the byte at offset 0x48, leaving bit 0
untouched during write operations.
Cells without the 'bits' property continue to work unchanged, ensuring
backward compatibility with existing device trees.
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Qualcomm PMICs include SDAM (Shared Direct Access Memory) regions which are used to store persistent data like reboot reasons that must survive across reboots. Without this driver, U-Boot cannot access PMIC storage, preventing reboot-to-bootloader functionality and other features that rely on persistent state. Add qcom-spmi-sdam driver that: - Probes SDAM regions from device tree compatible "qcom,spmi-sdam" - Implements NVMEM provider interface for standard cell-based access - Uses SPMI register read/write operations for data access This enables reboot-mode and other subsystems to access PMIC storage through standard NVMEM APIs. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add REBOOT_MODE_ENV_UPDATE Kconfig option and implement automatic reboot-mode env variable update at last stage init. When enabled, the reboot-mode uclass registers an EVT_LAST_STAGE_INIT event handler that probes the first reboot-mode device and calls dm_reboot_mode_update() to set the reboot-mode environment variable. EVT_LAST_STAGE_INIT fires after the environment is fully initialized. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Update preboot to check the reboot-mode environment variable and automatically enter fastboot mode when the reboot reason is "bootloader". This enables 'adb reboot bootloader' functionality on Qualcomm platforms. The reboot-mode variable is set by the reboot-mode uclass via EVT_LAST_STAGE_INIT before preboot runs. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Enable reboot-mode functionality for all Qualcomm platforms that define reboot-mode device tree nodes. The drivers gracefully handle platforms without reboot-mode configuration, making it safe to enable globally. Add config options: CONFIG_DM_REBOOT_MODE=y - Core reboot-mode framework CONFIG_REBOOT_MODE_NVMEM=y - NVMEM-based storage backend CONFIG_QCOM_SPMI_SDAM=y - Qualcomm PMIC SDAM/PON access CONFIG_REBOOT_MODE_ENV_UPDATE=y - Auto-update reboot-mode env Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add a mock I2C EEPROM device (nvmem-test@50) to the sandbox device tree to support NVMEM bit field operation testing. Add test coverage for NVMEM bit field read and write operations to validate the new bit field support in the NVMEM subsystem. Test cases include: - 1-byte cell with 7-bit field (Qualcomm SDAM reboot reason use case) - 2-byte cell with 12-bit field spanning a byte boundary - 4-byte cell without a bit field (legacy byte-level access) - 4-byte cell with a 16-bit field in the upper 2 bytes Error validation tests cover: - Bit field exceeding the cell size - Bit field exceeding the 32-bit maximum - Invalid bit_offset and nbits combinations - Buffer size mismatch in non-bit-field mode The tests verify: - Correct bit extraction during read operations - Read-modify-write behavior preserving unrelated bits - Proper error handling for invalid configurations Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Update the nvmem_cell_read() and nvmem_cell_write() documentation to describe the new bit field operation mode. The documentation now clearly explains: For bit field mode (nbits > 0): - Read: extracts the bit field from raw hardware bytes - Write: performs read-modify-write to preserve other bits - Requirements: buffer size must be sizeof(u32), cell size <= 4 bytes For non-bit-field mode (nbits == 0): - Read/Write: direct byte-level access - Requirements: buffer size must equal the cell size This helps developers understand when to use each mode and the associated buffer size requirements. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
The PM8150 PMIC on this platform uses the older PON (Power On) register architecture rather than dedicated SDAM regions found in newer PMIC generations. To enable reboot-mode functionality with the unified NVMEM-based approach, add a compatibility wrapper that exposes PON registers through the SDAM NVMEM interface. Add device tree configuration: - NVMEM node with compatible "qcom,spmi-sdam" wrapping PON registers - Uses 'ranges' property to map the PON register block at offset 0x800 - NVMEM cell at offset 0x8F (PON_SOFT_RB_SPARE register) - 7-bit field (bits [7:1]) for reboot reason, preserving bit 0 - Mode mappings: bootloader=0x02, recovery=0x01 This wrapper allows the SDAM NVMEM driver to access PON registers transparently, providing a unified interface for both PON-based (older) and SDAM-based (newer) PMIC generations. The PON_SOFT_RB_SPARE register persists across warm resets and is automatically cleared on power cycle. This will be maintained in uboot untill it is upstreamed in kernel dts Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Reorder compatible strings in stub_clk_ids to maintain alphabetical order for easier maintenance. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add RPMH clock compatible strings for QCS615 and SA8775P SoCs to enable clock framework support on these platforms. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add UFS clock support for SA8775P including register definitions, rate configuration, and gate clocks. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add UFS clock support for qcs615 including register definitions, rate configuration, and gate clocks. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add UFS clock support for sc7280 including register definitions, rate configuration, and gate clocks. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Move UFS clock initialization and enabling before hardware setup to ensure clocks are running when accessing UFS registers. Previously, U-Boot depended on earlier bootloader stages to initialize UFS clocks. When these bootloaders failed to do so, UFS registers became inaccessible, causing initialization to fail. This change makes U-Boot initialize and enable UFS clocks early in the init sequence, removing the dependency on previous bootloaders. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE correctly enables the device reference clock. The second call after ufs_qcom_advertise_quirks() is redundant as the clock is already enabled. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Implement device selection syntax allowing users to specify the target block device using "N:partition" format, where N is the device number. When no device is specified, the default from CONFIG_FASTBOOT_FLASH_BLOCK_DEVICE_ID is used. Modify fastboot_block_get_part_info() to use the new parsing function, enabling operations like "fastboot flash 0:boot boot.img" to write to specific devices while maintaining backward compatibility with the existing "fastboot flash boot boot.img" syntax. Example usage: fastboot flash 0:boot boot.img # Flash to device 0 fastboot flash 1:system system.img # Flash to device 1 fastboot flash boot boot.img # Use default device Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add fastboot_flash_gpt_partition_table() and fastboot_flash_mbr_partition_table() helper functions that handle flashing of GPT and MBR partition tables to block devices. The MMC backend now uses these helper functions for GPT and MBR operations, simplifying the code while maintaining the same functionality. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add support for flashing GPT and MBR partition tables to the fastboot block backend. This enables operations like "fastboot flash gpt gpt.img" and "fastboot flash mbr mbr.img" for block devices. The implementation validates partition table names and rejects invalid input formats such as ":gpt" or ":mbr" where the device prefix is missing. Valid formats include "gpt", "mbr", "0:gpt", and "1:mbr". Update Kconfig dependencies to allow FASTBOOT_GPT_NAME and FASTBOOT_MBR_NAME to work with both MMC and block backends.` Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add documentation for the device selection syntax in fastboot block device operations. Users can now specify target devices using "N:partition" format where N is the device number. Document usage examples for regular partition operations like "fastboot flash 0:boot boot.img" and partition table operations like "fastboot flash 1:gpt gpt.img". When no device number is specified, the default from CONFIG_FASTBOOT_FLASH_BLOCK_DEVICE_ID is used. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Rename qcom_qcs9100_defconfig to qcom_lemans_defconfig and update the defconfig to select lemans-evk DTS instead of qcs9100-ride-r3. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Replace MMC-specific fastboot flash configuration with generic block device support for Qualcomm platforms. This change switches from MMC device 0 to SCSI interface with device ID 4, enabling fastboot operations on UFS storage instead of eMMC. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Introduce part_get_info_by_type_guid() function to enable partition lookup using partition type GUID. This complements the existing UUID lookup functionality and provides more flexible partition discovery mechanisms. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Introduce scsi_get_blk_by_type_guid() function to enable SCSI partition discovery using partition type GUID. This function scans all available SCSI devices and searches for a partition matching the specified type GUID. Reviewed-by: Simon Glass <simon.glass@canonical.com> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Compute blk_find_max_devnum(UCLASS_SCSI) only once instead of on every loop iteration for better performance. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Change the default value from integer 0 to string "0" to match the string type of the configuration option. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add support for locating SCSI environment partition using GPT type GUID. Introduce a Kconfig choice statement to select between three mutually exclusive partition lookup methods: UUID-based (default), type GUID-based, and hardware partition number. Reorganize existing configs to depend on their respective choice options. Update ENV_IS_IN_SCSI help text to document the new configuration structure. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Update env/scsi.c to support the new partition selection methods introduced in the Kconfig. Replace runtime string checks with compile-time preprocessor conditionals. Implement support for all three partition selection methods: - TYPE_GUID: Uses scsi_get_blk_by_type_guid() - UUID: Uses scsi_get_blk_by_uuid() - HW: Uses blk_get_device_part_str() Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
The IPQ5210 boot ROM expects the SPL binary image to be embedded within an ELF along with additional binaries. Hence add the relevant commands and linker script needed to convert u-boot-spl.bin to the expected format. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Introduce a defconfig for the Qualcomm IPQ5210 SoC based RDPs. Presently supports eMMC. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Add details about the SPL & U-Boot proper build steps, converting to flashable images, source URLs for the needed binaries and scripts. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Add the U-Boot DTS overlay for the Lemans EVK board. Mark the required nodes with bootph-all to make them available in the SPL device tree. This covers the UFS host controller and PHY, GCC and RPMH clock controllers, Apps RSC, UART10 console, and the TLMM GPIO controller. A static memory layout is defined temporarily until the changes to get memory information from SMEM ([1]) gets merged. [1] https://lore.kernel.org/u-boot/20260504-b4-modernise-smem-v2-0-c01ec2ff3886@linaro.org/ Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add SPL defconfig for the Lemans EVK board. The SPL loads a FIT image containing TF-A, OP-TEE and U-Boot proper from the "uefi_a" UFS partition and hands off to TF-A. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
The SPL code unconditionally reads pbl_shared_data from r0 and invokes PBL-specific loaders, assuming SPL is always loaded directly by PBL. This fails when XBL is used as an intermediate loader (in Schneider Lemans case), where r0 does not carry valid PBL data. Introduce SPL_QCOM_BOOT_FROM_PBL (default y) to guard PBL-specific behavior in save_boot_params(), spl_boot_device(), and board_init_f(). This includes the pre-DDR init sequence (qcom_spl_loader_pre_ddr() and qclib_post_process_from_spl()), which is skipped when XBL has already initialized DDR. Also fix the smem.h include path to use the canonical soc/qcom/ prefix and add a mem_map global definition. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
The Lemans platform boots via XBL as an intermediate loader between PBL and U-Boot SPL. Since SPL_QCOM_BOOT_FROM_PBL defaults to y, explicitly disable it in qcom_lemans_spl_defconfig to prevent the SPL from attempting to parse PBL shared data from r0 and running the pre-DDR init sequence already handled by XBL. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add CONFIG_QCOM_SNAGBOOT_MODE to enable snagboot mode on Qualcomm platforms. This config automatically selects the required dependencies. Add QCOM_BOOT0_SNAGBOOT_MODE as boot0.h config for automatic selection by QCOM_SNAGBOOT_MODE. Document the platform-specific requirements and configs that must be disabled in snagboot mode. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
In snagboot mode, there is no PSCI firmware and U-Boot will crash if it attempts to make PSCI calls so disable it in this case. Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
In snagboot mode, U-Boot is loaded directly by XBL without PSCI firmware support. The functions show_psci_version() and qcom_psci_fixup() call arm_smccc_smc() which is unavailable when CONFIG_ARM_SMCCC is disabled, causing build failures. Hence, added CONFIG_ARM_SMCCC guards to both functions. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
When U-Boot is loaded by XBL in Snagboot mode, XBL leaves the MMU enabled with its own page tables. This causes stale TLB entries and incorrect memory mappings when U-Boot initializes its own MMU. Disable the MMU and invalidate TLBs before branching to the reset vector. This ensures a clean MMU state for U-Boot initialization in Snagboot mode. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
In snagboot mode, XBL loads U-Boot directly without populating CMD DB. The cmd-db driver fails to bind when CMD DB magic is invalid, blocking boot even when CMD DB is not strictly required. Use QCOM_SNAGBOOT_MODE config to allow the driver to bind successfully when CMD DB data is absent. When QCOM_SNAGBOOT_MODE is enabled and CMD DB data is present, we log a warning. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add defconfig for booting U-Boot in Snagboot mode on Lemans-EVK. In this mode, XBL loads U-Boot directly into DDR and U-Boot enters fastboot over USB for device provisioning. Create a reusable config fragment at configs/qcom-snagboot.config with common snagboot settings. Platform-specific defconfigs should include this fragment along with their own settings. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add documentation for snagboot mode support on Qualcomm platforms. This covers the architecture, execution flow, and board enablement requirements. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add PHASE_ prefix to QCOM_SPMI_SDAM config for phase-aware builds. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Remove hardcoded memory node as memory configuration is now dynamically read from SMEM. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Remove CONFIG_TEXT_BASE and CONFIG_REMAKE_ELF from lemans SPL defconfig as they are not needed for FIT-based U-Boot loading. The load address is handled by the FIT image configuration. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
…resses Shikra uses a different TCSR base address than the hardcoded value (0x01fc8000), causing a crash when reading the SOC_HW_VERSION register. Fix this by replacing the hardcoded TCSR address with a per-SoC lookup table (qcom_soc_table) that stores both shared IMEM cookie addresses and TCSR SOC_HW_VERSION register addresses for each supported SoC. The table stores full register addresses (TCSR_BASE + 0x8000 offset) to avoid runtime calculations. Addresses are looked up by matching the root DTS compatible string against table entries. This is a workaround and proper fix to fetch the addr from dts needs to be identified & upstreamed Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
This reverts commit 50231e9. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
The driver reads ownership registers from the wrong address for V5. The ownership table is at offset 0x700 from spmi_cnfg base, not 0x0. This causes incorrect peripheral ownership detection and potential access violations. Add the missing 0x700 offset to match the kernel driver [1] [1] https://github.com/torvalds/linux/blob/4b99990cdf9560e8a071640baf19f312e6ae02f4/drivers/spmi/spmi-pmic-arb.c#L1737 Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
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I see this commit getting a NAK upstream, please incorporate upstream feedback. |
When CONFIG_SKIP_EARLY_DM is enabled and no clock driver is available during early serial init, devm_clk_get_optional() returns an error pointer. The original code attempted to enable this error pointer, causing a crash. Fix by checking for both error pointers and NULL before calling clk_enable(), using IS_ERR_OR_NULL() to handle all cases properly. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Enable CONFIG_SKIP_EARLY_DM to skip device model initialization during pre-relocation phase, improving boot time by around 50% by deferring device probing until after relocation Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add a FIT (Flattened Image Tree) image template for Qualcomm platforms that use SPL to load a complete boot chain with pre-DDR and post-DDR stages. Pre-DDR initialization components (pre-ddr-config): - QC Config segments (qcconfig_1-4, qcconfig-meta) - QC Lib segments (qclib_1-2, qclib-meta) Post-DDR components (post-ddr-config): - ARM Trusted Firmware (TF-A/BL31) - OP-TEE (BL32) - U-Boot proper (BL33) The FIT image can be built using: mkimage -f board/qualcomm/fit_spl.its fit_spl.itb The default configuration is set to post-ddr config for standard boot flow, with pre-ddr config available for platforms requiring early DDR initialization. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Replace the abort-only RX initialization with a proper stop sequence that matches the Linux driver approach. The new qcom_geni_serial_stop_rx_fifo function sends a CANCEL command instead of immediately aborting, waits for completion, drains any remaining FIFO data if S_RX_FIFO_LAST_EN is set, and only sends ABORT as a fallback if the secondary sequencer remains active after cancellation. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add IRQ status validation to distinguish legitimate UART data from electrical noise in the RX FIFO. When the UART cable is disconnected, the floating RX line can pick up noise that the GENI hardware interprets as valid data and places in the FIFO. So, check the RX IRQ status register for RX watermark or last flags before reporting pending data. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
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addressed Casey' comments and pushed v2: https://lore.kernel.org/u-boot/20260707-uart-v2-0-d38277b6c4ce@oss.qualcomm.com/ |
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The GENI UART hardware can retain stale data in the RX FIFO. The msm_serial_pending() function was reporting this stale data as pending input, causing U-Boot to incorrectly assume a key press and stop at the CLI prompt instead of continuing the boot process.
Add IRQ status validation to distinguish between legitimate received data and stale FIFO contents. Check the Secondary IRQ status register for RX watermark or last flags before reporting pending data. If the FIFO contains data but no valid IRQ flags are set, ignore it as stale.
Upstream link: https://lore.kernel.org/u-boot/20260629-uart-v1-1-cbc46fe1d7d3@oss.qualcomm.com/