[qcom-next] arm: dts: talos: Disable SD card controller

MAINTAINERS

@@ -688,7 +688,6 @@ F:	drivers/phy/msm8916-usbh-phy.c
 F:	drivers/phy/qcom/
 F:	drivers/serial/serial_msm.c
 F:	drivers/serial/serial_msm_geni.c
-F:	drivers/smem/msm_smem.c
 F:	drivers/spmi/spmi-msm.c
 F:	drivers/usb/host/ehci-msm.c
 N:	qcom

arch/arm/Kconfig

@@ -1140,9 +1140,8 @@ config ARCH_SNAPDRAGON
 	select DM_RESET
 	select POWER_DOMAIN
 	select GPIO_EXTRA_HEADER
-	select MSM_SMEM
 	select OF_CONTROL
-	select SMEM
+	select QCOM_SMEM
 	select SPMI
 	select BOARD_LATE_INIT
 	select OF_BOARD

arch/arm/cpu/armv8/cache_v8.c

@@ -163,7 +163,7 @@ u64 get_tcr(u64 *pips, u64 *pva_bits)
 
 static int pte_type(u64 *pte)
 {
-	return *pte & PTE_TYPE_MASK;
+	return *pte & PTE_TYPE_VALID ? *pte & PTE_TYPE_MASK : PTE_TYPE_FAULT;
 }
 
 /* Returns the LSB number for a PTE on level <level> */
@@ -388,13 +388,18 @@ static void map_range(u64 virt, u64 phys, u64 size, int level,
 	}
 }
 
-void mmu_map_region(phys_addr_t addr, u64 size, bool emergency)
+void mmu_map_region(phys_addr_t addr, u64 size, bool cached, bool emergency)
 {
 	u64 va_bits;
 	int level = 0;
-	u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE;
+	u64 attrs;
 
-	attrs |= PTE_TYPE_BLOCK | PTE_BLOCK_AF;
+	if (cached)
+		attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL);
+	else
+		attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC);
+
+	attrs |= PTE_BLOCK_INNER_SHARE | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
 
 	get_tcr(NULL, &va_bits);
 	if (va_bits < 39)
@@ -940,6 +945,18 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
 	u64 levelsize = 1ULL << levelshift;
 	u64 *pte = find_pte(start, level);
 
+	/*
+	 * If we're trying to unmap a region then check if it's already unmapped or if it's bigger
+	 * then the PTE we're looking at right now, in the first case we can do nothing and in the
+	 * second case we just need to unmap this page/block.
+	 * Otherwise we will needlessly create new tables until we have traversed every single page
+	 * in the region.
+	 */
+	if (attrs == PTE_TYPE_FAULT && (pte_type(pte) == PTE_TYPE_FAULT || size >= levelsize)) {
+		*pte &= ~(PMD_ATTRMASK | PTE_TYPE_MASK);
+		return levelsize;
+	}
+
 	/* Can we can just modify the current level block PTE? */
 	if (is_aligned(start, size, levelsize)) {
 		if (flag) {
@@ -1082,6 +1099,10 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
 			   gd->arch.tlb_addr + gd->arch.tlb_size);
 	__asm_invalidate_tlb_all();
 
+	/* If we were unmapping a region then we're done! */
+	if (attrs == PTE_TYPE_FAULT)
+		return;
+
 	mmu_change_region_attr_nobreak(addr, siz, attrs);
 }
 

arch/arm/dts/qcs615-ride-u-boot.dtsi

@@ -11,4 +11,30 @@
 		      <0x0 0xc0000000 0x0 0xc0000000>,
 		      <0x1 0x80000000 0x1 0x00000000>;
 	};
+
+	reboot-mode {
+		compatible = "nvmem-reboot-mode";
+		nvmem-cells = <&reboot_reason>;
+		nvmem-cell-names = "reboot-mode";
+
+		mode-bootloader = <0x02>;
+		mode-recovery   = <0x01>;
+	};
+};
+
+&pm8150_0 {
+	/* Virtual NVMEM node for PON-based reboot reason storage */
+	nvram@800 {
+		compatible = "qcom,spmi-sdam";
+		reg = <0x800>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x800 0x100>;
+
+		/* Reboot reason cell at PON_SOFT_RB_SPARE (0x88F) */
+		reboot_reason: reboot-reason@8f {
+			reg = <0x8f 0x1>;
+			bits = <1 7>;
+		};
+	};
 };

arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi

@@ -3,21 +3,29 @@
  * Copyright (c) 2024 Linaro Ltd.
  */
 / {
-	/* When running as the primary bootloader there is no prior
-	 * stage to populate the memory layout for us. We *should*
-	 * have two nodes here, but ABL does NOT like that.
-	 * sooo we're stuck with this.
-	 */
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0x3A800000>,
-		      <0 0xC0000000 0 0x01800000>,
-		      <0 0xC3400000 0 0x3CC00000>,
-		      <1 0x00000000 1 0x00000000>;
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		axon_dma_mem: axon-dma@80600000 {
+			reg = <0x0 0x80600000 0x0 0x100000>;
+			no-map;
+		};
+
+		xbl_dt_mem: xbl-dt@80894000 {
+			reg = <0x0 0x80894000 0x0 0x40000>;
+			no-map;
+		};
+
+		pil_reserved_mem: pil-reserved@84300000 {
+			reg = <0x0 0x84300000 0x0 0x16b00000>;
+			no-map;
+		};
+
+		display_mem: display@e1000000 {
+			reg = <0x0 0xe1000000 0x0 0x2400000>;
+			no-map;
+		};
 	};
 };
-
-// RAM Entry 0 : Base 0x0080000000  Size 0x003A800000
-// RAM Entry 1 : Base 0x00C0000000  Size 0x0001800000
-// RAM Entry 2 : Base 0x00C3400000  Size 0x003CC00000
-// RAM Entry 3 : Base 0x0100000000  Size 0x0100000000

arch/arm/dts/talos-evk-u-boot.dtsi

@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hyp_mem: hyp@80000000 {
+			reg = <0x0 0x80000000 0x0 0x600000>;
+			no-map;
+		};
+
+		xbl_boot_mem: xbl-boot@85d00000 {
+			reg = <0x0 0x85d00000 0x0 0x200000>;
+			no-map;
+		};
+
+		aop_mem: aop@85f00000 {
+			reg = <0x0 0x85f00000 0x0 0x20000>;
+			no-map;
+		};
+
+		xbl_dt_mem: xbl-dt@85f40000 {
+			reg = <0x0 0x85f40000 0x0 0x30000>;
+			no-map;
+		};
+
+		tz_stat_mem: tz-stat@86200000 {
+			reg = <0x0 0x86200000 0x0 0x100000>;
+			no-map;
+		};
+
+		tags_mem: tags@86300000 {
+			reg = <0x0 0x86300000 0x0 0x1200000>;
+			no-map;
+		};
+
+		tz_mem: tz@87500000 {
+			reg = <0x0 0x87500000 0x0 0x500000>;
+			no-map;
+		};
+
+		tzapps_mem: tzapps@87a00000 {
+			reg = <0x0 0x87a00000 0x0 0x1c00000>;
+			no-map;
+		};
+
+		pil_mem: pil@8ab00000 {
+			reg = <0x0 0x8ab00000 0x0 0xcc17000>;
+			no-map;
+		};
+
+		secure_dsp_mem: secure-dsp@a0000000 {
+			reg = <0x0 0xa0000000 0x0 0x1600000>;
+			no-map;
+		};
+	};
+};
+
+/* Disable SD card controller */
+&sdhc_2 {
+	status = "disabled";
+};

arch/arm/include/asm/system.h

@@ -306,9 +306,10 @@ void flush_l3_cache(void);
  *
  * @start: Start address of the region
  * @size: Size of the region
+ * @cached: Map memory as cacheable or not
  * @emerg: Also map the region in the emergency table
  */
-void mmu_map_region(phys_addr_t start, u64 size, bool emerg);
+void mmu_map_region(phys_addr_t start, u64 size, bool cached, bool emerg);
 
 /**
  * mmu_change_region_attr() - change a mapped region attributes

arch/arm/mach-snapdragon/Kconfig

@@ -42,4 +42,35 @@ config SYS_CONFIG_NAME
 	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
 	  will be used for board configuration.
 
+config QCOM_FIT_MULTIDTB
+	bool "Enable FIT multi-DTB selection for Qualcomm platforms"
+	depends on FIT
+	help
+	  Enable FIT multi-DTB selection for Qualcomm platforms.
+	  This allows U-Boot to select the appropriate device tree
+	  from a FIT image.
+
+choice
+	prompt "Qualcomm boot0.h workaround"
+	optional
+	help
+	  While U-Boot on Qualcomm platforms doesn't generally need compile-time
+	  adjustments based on the target SoC, workarounds in boot0.h can't
+	  practically detect the SoC at runtime. Enable one of these workarounds
+	  if you know you need it.
+
+config BOOT0_MSM8916_PSCI_WORKAROUND
+	bool "boot0.h workaround for buggy PSCI on the msm8916 SoC"
+	help
+	  Select this if you are building U-Boot proper for an msm8916 board that
+	  uses the buggy PSCI implementation.
+
+config QCOM_EL2_GUNYAH_EXIT_SUPPORT
+	bool "Enable early EL2 switch by exiting Gunyah"
+	help
+	  Exit Gunyah hypervisor and switch to EL2 during early boot. This must
+	  happen before EL register configuration in start.S so that U-Boot can
+	  run properly at EL2.
+endchoice
+
 endif

arch/arm/mach-snapdragon/Makefile

@@ -2,6 +2,7 @@
 #
 # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 
-obj-y += board.o
+obj-y += board.o dram.o
 obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += capsule_update.o
 obj-$(CONFIG_OF_LIVE) += of_fixup.o
+obj-$(CONFIG_QCOM_FIT_MULTIDTB) += qcom_fit_multidtb.o