arm64: dts: qcom: nord: Add adreno and PCIe SMMU nodes - #1648
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Bibek Kumar Patro (bibekpatro) wants to merge 1642 commits into
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arm64: dts: qcom: nord: Add adreno and PCIe SMMU nodes#1648Bibek Kumar Patro (bibekpatro) wants to merge 1642 commits into
Bibek Kumar Patro (bibekpatro) wants to merge 1642 commits into
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On Nord's HS-only USB20 tile the QSCRATCH register interface is clocked by the eUSB2 PHY's UTMI clock. Writing the select-utmi-as-pipe-clk configuration from probe() happens before the PHY is initialized and faults with a synchronous external abort. Add per-compatible data to the driver. Initially it contains the defer_utmi_clk_sel flag - set it for qcom,nord-dwc3 - which tells the driver to request an early PHY init from DWC3 core. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
The NE_GCC block has two eUSB2 PHY block resets - PRIM and SEC - but right now only the primary is registered. Add the secondary, which is required by the usb_1 eUSB2 PHY. Note that the SoC has three eUSB2 PHYs but only these two QUSB2PHY resets: the HS-only USB20 tile has no dedicated QUSB2PHY reset and is instead reset as a whole via NE_GCC_USB20_PRIM_BCR. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Add the secondary USB2 PHY reset in order to enable the USB nodes in DTS for Nord Ride SX. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
The three eUSB2 PHY register ranges are reached through an AHB2PHY bridge in the NE_GCC tile. The bridge comes out of power-on with its block in reset asserted and its clock disabled. Nothing else on the SoC brings it up. Any access to a PHY config register in that state aborts with a synchronous external abort. Deassert the bridge reset and enable the clock in probe(). Mark the clock CLK_IGNORE_UNUSED so that clk_disable_unused() does not disable it again. No driver claims it as a consumer, since the bridge is transparent to the PHY drivers. Neither the reset nor the clock is exposed through the driver's reset/clock maps: doing so would let consumers control them individually, which is not how the hardware is meant to be used (the bridge must be up before any PHY driver can probe). Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
We use the hw_clk_ctrl flag on six USB31 RCGs. Other Qualcomm GCC drivers do this for USB but on Nord the firmware does not bring the USB block out of reset nor drive the clock-request handshake. Drop hw_clk_ctrl from all six so the RCGs are driven purely from software Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
ne_gcc_usb3_{prim,sec}_phy_aux_clk and _com_aux_clk never report
CLK_OFF=0 even with their RCG root running, so clk_branch_wait()
times out and the combo PHY fails to initialize.
Use BRANCH_HALT_SKIP for these four branches, as already done for the
pipe clocks in this driver.
Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Add the SPMI PMIC Arbiter node for the Nord platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Add the base nodes for the three DWC3 USB controllers. These carry only the SoC-invariant properties and are disabled by default. The extension for the embedded Nord variant and relevant board files will add the platform resources and enable them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
…s and PHYs Add the platform resources for the USB controllers on the embedded Nord variant: clocks, resets, power domains and interconnect paths. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Add the PMIC dtsi for Nord. Initially describe the two pmm8654au SPMI PMICs. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Enable the USB controllers, their PHYs and wire up the repeaters. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
With meta_8_3 build, usb_1/2 causes SMMU error like below. Disable them for now. [ 1.357502] Internal error: synchronous external abort: 0000000096000010 [qualcomm-linux#1] SMP ... [ 1.357536] Call trace: [ 1.357537] arm_smmu_write_sme+0x74/0x98 (P) [ 1.357539] arm_smmu_probe_device+0x25c/0x400 [ 1.357540] __iommu_probe_device+0xf4/0x4bc [ 1.357542] probe_iommu_group+0x3c/0x68 [ 1.357544] bus_for_each_dev+0x7c/0xdc [ 1.357546] iommu_device_register+0xd8/0x244 [ 1.357548] arm_smmu_device_probe+0xc98/0xf14 [ 1.357549] platform_probe+0x5c/0x9c [ 1.357550] really_probe+0xbc/0x29c [ 1.357552] __driver_probe_device+0x16c/0x19c [ 1.357555] driver_probe_device+0x3c/0x114 [ 1.357557] __driver_attach+0x90/0x180 [ 1.357559] bus_for_each_dev+0x7c/0xdc [ 1.357561] driver_attach+0x24/0x30 [ 1.357563] bus_add_driver+0xe4/0x208 [ 1.357565] driver_register+0x5c/0x124 [ 1.357566] __platform_driver_register+0x28/0x34 [ 1.357567] arm_smmu_init+0x30/0x74 [ 1.357572] do_one_initcall+0x80/0x1c8 [ 1.357574] kernel_init_freeable+0x208/0x2f0 [ 1.357576] kernel_init+0x2c/0x1e0 [ 1.357580] ret_from_fork+0x10/0x20 [ 1.357582] Code: f9400404 b5000104 f9400680 8b22c002 (b9000043) [ 1.357583] ---[ end trace 0000000000000000 ]--- Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable USB_0 on the RRD board with PTN3222 eUSB2 redriver on I2C9. Although FUSB15201 Type-C controller driver is missing, enabling usb-role-switch and "otg" mode still make it easier to test both host and device mode, by manually switching the mode via: /sys/kernel/debug/usb/a600000.usb/mode Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable OTG mode for USB_0 so that ADB over USB can work. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…tach qcom_pas_attach() unmasks the handover IRQ and marks handover_issued even though this driver instance never runs qcom_q6v5_prepare() for the boot it is attaching to. This was believed necessary to flush a stale interrupt latched at the interrupt controller while masked, but the handover IRQ is a Qualcomm SMP2P soft IRQ, not a real edge-latched hardware interrupt. The Linux SMP2P driver updates its cached value unconditionally on every notification and only delivers the nested IRQ for bits currently enabled in its own software bitmap, so a transition that happens while masked is simply dropped, never replayed on a later unmask. Since there is nothing to flush, and this driver instance never takes the proxy power-domain/clock/regulator votes that the handover callback would tear down, there is no need to unmask the IRQ in attach() at all. Drop the enable_irq()/disable_irq() pair; setting handover_issued = true is sufficient to keep the flag consistent for the eventual qcom_q6v5_unprepare()/qcom_q6v5_prepare() cycle. It fixes the following unbalanced runtime PM usage and IRQ enable warnings seen on Nord ADSP (probed as attached), after commit bb7c5d6 ("remoteproc: qcom: q6v5: Make handover IRQ one-shot") comes in place. root@iq10-rrd:~# cat /sys/class/remoteproc/remoteproc0/state attached root@iq10-rrd:~# echo stop > /sys/class/remoteproc/remoteproc0/state [ 40.004874] genpd genpd:0:4c00000.remoteproc: Runtime PM usage count underflow! [ 40.012409] genpd genpd:1:4c00000.remoteproc: Runtime PM usage count underflow! [ 40.050074] remoteproc remoteproc0: stopped remote processor adsp root@iq10-rrd:~# echo start > /sys/class/remoteproc/remoteproc0/state [ 44.350298] remoteproc remoteproc0: powering up adsp [ 44.375769] remoteproc remoteproc0: Booting fw image qcom/nord/adsp.mbn, size 8241816 [ 44.389850] PDM: no support for the platform, userspace daemon might be required. [ 44.397864] ------------[ cut here ]------------ [ 44.402633] Unbalanced enable for IRQ 363 [ 44.406779] WARNING: kernel/irq/manage.c:775 at __enable_irq+0x4c/0x7c, CPU#9: sh/791 ... Suggested-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20260801011731.1084591-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add device tree nodes to support ADSP (HPASS DSP) and CDSPs remoteproc on Nord SoC. This includes: - SMEM memory reservation used by the inter-processor communication infrastructure - IPCC mailbox controller for inter-processor signalling - AOSS QMP node for load state power management - SMP2P nodes providing stop control and fault/crash interrupt signals - Remoteproc nodes with a GLINK edge and FastRPC compute contexts for userspace offload The embedded variant specific power domains, XO clock, and interconnect paths are filled in nord-embedded.dtsi. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord RRD board. Due to a known issue, the first two or three CDSPs being probed may fail to boot up. A manual start can bring some of them out of reset. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord Ride Embedded board. Due to a known issue, the first two or three CDSPs being probed may fail to boot up. A manual start can bring some of them out of reset. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add cooling-cells for all 18 CPUs, so every cluster's cpufreq cooling device will show up in sysfs and userspace can take the full control of them. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances and the PCIe SMMU (SMMUv3) nodes. Wire up the gpucc clock and power domain on both adreno SMMU nodes in nord-embedded.dtsi for embedded Nord variants where gpucc is available. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
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Add the QCOM IOMMU debug/testing framework (CONFIG_QCOM_IOMMU_DEBUG) with debugfs-based profiling and ATOS testing support. Add the iommu_test_device node to nord-rrd using apps_smmu_0 SID 0x0001 which is reserved for IOMMU debug use. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
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Add the Adreno GPU SMMU (MMU-500) and PCIe SMMU (SMMUv3) nodes.