WORKAROUND: Add qref and refgen regulator support for QCS8300 and SA8775p PCIe PHYs - #1611
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…oth USB and UART On Hamoa boards, a single M.2 slot may host either a UART-based or a USB-based Bluetooth device. As a result, the UART controller node is always present in DT, while the USB path is hot-pluggable. When Bluetooth operates over USB, the presence of the UART DT node still causes the hci_qca UART driver to probe. During probe or power sequencing, the driver may deassert BT_EN, cutting power to the shared Bluetooth device and disconnecting the USB interface. Model BT_EN as an always-on fixed regulator so it cannot be toggled by the UART probe. This prevents the UART driver from interfering with Bluetooth operation when the device is connected over USB. Workaround will be reverted once the M.2 solutionis available upstream. Signed-off-by: Shuai Zhang <shuai.zhang@oss.qualcomm.com>
…nable GPIO If a Bluetooth consumer device does not have a bt-enable GPIO configured in the power sequencer (for example, when BT_EN is tied high via a hardware pull-up and therefore absent from the DT), the power sequencer should not match the device. In this case, the Bluetooth consumer driver will fall back to its legacy power control path and correctly set power_ctrl_enabled to false. Bluetooth device nodes are conventionally named "bluetooth" in the device tree, so use of_node_name_eq() as a generic check instead of enumerating specific compatible strings. Workaround will be reverted once the M.2 solution is available upstream. Signed-off-by: Shuai Zhang <shuai.zhang@oss.qualcomm.com>
Bootup crash seen on kaanapali-mtp board. [ 8.114249][ C0] [drm:dpu_encoder_frame_done_timeout:2731] [dpu error]enc33 frame done timeout [ 8.116480][ T284] Unable to handle kernel paging request at virtual address ffff800080e5e000 [ 8.116488][ T284] Mem abort info: [ 8.116492][ T284] ESR = 0x0000000096000007 [ 8.116497][ T284] EC = 0x25: DABT (current EL), IL = 32 bits [ 8.116502][ T284] SET = 0, FnV = 0 [ 8.116507][ T284] EA = 0, S1PTW = 0 [ 8.116511][ T284] FSC = 0x07: level 3 translation fault [ 8.116516][ T284] Data abort info: [ 8.116519][ T284] ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000 [ 8.116524][ T284] CM = 0, WnR = 0, TnD = 0, TagAccess = 0 [ 8.116529][ T284] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0 [ 8.116535][ T284] swapper pgtable: 4k pages, 48-bit VAs, pgdp=00000009bf36c000 [ 8.116541][ T284] [ffff800080e5e000] pgd=0000000000000000, p4d=1000000880346403, pud=1000000880347403, pmd=1000000881e2d403, pte=0000000000000000 [ 8.116567][ T284] Internal error: Oops: 0000000096000007 [qualcomm-linux#1] SMP Revert the change for now to unblock. This reverts commit b0907ee. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…oth USB and UART On Purwa boards, a single M.2 slot may host either a UART-based or a USB-based Bluetooth device. As a result, the UART controller node is always present in DT, while the USB path is hot-pluggable. When Bluetooth operates over USB, the presence of the UART DT node still causes the hci_qca UART driver to probe. During probe or power sequencing, the driver may deassert BT_EN, cutting power to the shared Bluetooth device and disconnecting the USB interface. Model BT_EN as an always-on fixed regulator so it cannot be toggled by the UART probe. This prevents the UART driver from interfering with Bluetooth operation when the device is connected over USB. Workaround will be reverted once the M.2 solutionis available upstream. Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
…es for Monaco The PCIe QMP PHYs on Monaco (QCS8300) require stable reference voltage provided by refgen and reference clock provided by qref. The refgen and qref require power supplies. Add a new sa8775p_qmp_phy_vreg_l list with vdda-qref and vdda-refgen supplies, and use it for qcs8300_qmp_gen4x2, sa8775p_qmp_gen4x2 and sa8775p_qmp_gen4x4 PCIe PHY configurations. Workaround will be reverted once the vote qref regulator for PCIe available in upstream. Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
…fgen supplies for PCIe PHYs The PCIe QMP PHYs on QCS8300 require stable reference voltage provided by refgen and reference clock provided by qref. Add vdda-qref-supply and vdda-refgen-supply to pcie0_phy and pcie1_phy nodes on the qcs8300-ride board. Workaround will be reverted once the vote qref regulator for PCIe available in upstream. Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
…nable GPIO Add a bt_gpio_required flag to the per-platform data to indicate that a chip's BT enable path requires a dedicated GPIO. Only skip matching the "bluetooth" device node when this flag is set and bt_gpio is absent. Previously the bt_gpio check was applied unconditionally, which caused chips like WCN3990 that have no separate BT/WLAN enable pins by design to fail matching even when bt-enable GPIO is legitimately absent from the DT. Set bt_gpio_required for WCN6855 and WCN7850 which do require a dedicated BT enable GPIO. Signed-off-by: Shuai Zhang <shuai.zhang@oss.qualcomm.com>
Add the new compatible string for the QCC2072 BT SoC to the Qualcomm Bluetooth DT binding schema. Link: https://lore.kernel.org/all/20260529175342.3363935-1-yepuri.siddu@oss.qualcomm.com/ Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
QCC2072 is a BT/WiFi combo SoC that uses different firmware
filenames and requires no external voltage regulators, so add
it as a new SoC type.
The chip supports the wideband speech and valid LE states
capabilities. Its firmware is named using the "orn" prefix and
follows the standard rom-version-based scheme:
- qca/ornbtfw<ver>.tlv
- qca/ornnv<ver>.bin
These firmware files are already present in the linux-firmware
repository.
Link: https://lore.kernel.org/all/20260529175822.3366535-1-yepuri.siddu@oss.qualcomm.com/
Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
…2 industrial mezzanine Add DTS support for M.2 QCC2072 on Qualcomm qcs6490-rb3gen2 industrial mezzanine board. Link: https://lore.kernel.org/all/20260529180234.3373056-1-yepuri.siddu@oss.qualcomm.com/ Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
QCC2072 requires the NVM and calibration data to be delivered to the controller bundled together in an outer TLV of type 4. After loading the NVM file, load the calibration file (qca/ornbcscal<ver>.bin) and combine both into a single buffer with the outer TLV header before passing it to qca_tlv_check_data(). The outer TLV header encodes the combined payload length in the high 24 bits and type 4 in the low 8 bits of the type_len field. If the calibration file is unavailable, fall back to downloading the NVM alone. Link: https://lore.kernel.org/all/20260529180431.3373856-1-yepuri.siddu@oss.qualcomm.com/ Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
On compute targets, PCIe is dependent on the UEFI. In UEFI, when a PCIe link-up fails on a given root port, the default behavior is to power down that root port. The power-down sequence disables the PHY, removes all clock votes, and drops the Interconnect Bandwidth (ICB) votes that were applied in UEFI for that PCIe controller. The HLOS PCIe driver when probes the PCIe6 root port, but probe fails because the PHY is already powered down and there is no PHY bring-up sequence in HLOS for any controller. Since PCIe probe fails, the Interconnect driver's sync_state callback never gets invoked. As a result, the max boot votes applied to other peripherals are never released or reduced, keeping the system stuck at max bandwidth votes and causing the sync state errors observed, this also blocks XO shutdown. Fix this temporarly, by disabling pcie6 now as modem is not functional in this release. we will revert this after finding proper fix. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
…nule issue Qualcomm SMMU-500 has an issue with TLBIVA/TLBIVAL where only the base-page-size entry at the base IOVA is invalidated, leaving stale TLB entries for the rest of the range. This causes use-after-free: after dma_free_coherent() unmaps a large buffer, the device can still access freed physical memory through stale TLB entries. On FastRPC workloads this manifests as ADSP crashes when the ELF loader writes to a freed PA that has been reallocated. Force the TLB invalidation step granule to the minimum page size for all Qualcomm SMMU-500 domains, ensuring each page in the range is individually invalidated. The minimum page size from pgsize_bitmap is used rather than hardcoded 4K to correctly handle 16K and 64K granule configurations. This increases the number of TLB invalidation operations for large ranges, but correctness takes precedence. Signed-off-by: Prakash Gupta <prakash.gupta@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
…or QCS8300 and SA8775p PHY Add a new sa8775p_qmp_phy_vreg_l that includes vdda-phy, vdda-pll, vdda-qref, vdda-refgen and refgen supplies, and use it for QCS8300 and SA8775p PCIe PHY configurations. This avoids modifying sm8550_qmp_phy_vreg_l and breaking SM8550 and SM8650. Note that due to a hardware issue, QREF actually depends on refgen3 rather than refgen2 as documented; refgen3 is therefore voted manually via the refgen supply as a workaround. Fixes: a05b6d5 ("phy: qcom-qmp-pcie: add support for sa8775p") Fixes: ebf198f ("phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300") Link: http://shc-kerarch-hyd:8080/kernel_archive/20260703094224.990231-3-ziyue.zhang@oss.qualcomm.com/ Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
… PCIe PHYs The QMP PCIe PHYs on QCS8300 require dedicated qref and refgen voltage supplies for stable operation. Without these supplies, the system may occasionally crash. Add vdda-qref-supply and vdda-refgen-supply in the board files (QCS8300-RIDE, Monaco-EVK and Monaco-Arduino-Monza), and add refgen-supply in the SoC DTSI (monaco.dtsi) since refgen is an on-chip regulator shared across boards. The refgen supply votes for refgen3 as a workaround for a hardware issue where both QREF and the PCIe PHY are expected to depend on refgen2, but QREF actually depends on refgen3. Fixes: 33967ea ("arm64: dts: qcom: qcs8300-ride: enable pcie0 interface") Fixes: cdb613a ("arm64: dts: qcom: qcs8300-ride: enable pcie1 interface") Fixes: 41e2424 ("arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.") Fixes: 5238f4e ("arm64: dts: qcom: Add Monaco Monza SoM") Link: http://shc-kerarch-hyd:8080/kernel_archive/20260703094224.990231-4-ziyue.zhang@oss.qualcomm.com/ Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
… PCIe PHYs The QMP PCIe PHYs on SA8775p require dedicated qref and refgen voltage supplies for stable operation. Without these supplies, the system may occasionally crash. Add vdda-qref-supply and vdda-refgen-supply in the board files (Lemans-EVK, Lemans-RIDE, QCS9100-RIDE, QCS9100-RIDE-R3, SA8775P-RIDE and SA8775P-RIDE-R3), and add refgen-supply in the SoC DTSI (lemans.dtsi) since refgen is an on-chip regulator shared across boards. The refgen supply votes for refgen3 as a workaround for a hardware errata (see cover letter). Fixes: 94d7d37 ("arm64: dts: qcom: lemans-evk: Enable PCIe support") Fixes: 76326da ("arm64: dts: qcom: lemans: Refactor ride/ride-r3 boards based on daughter cards") Link: http://shc-kerarch-hyd:8080/kernel_archive/20260703094224.990231-5-ziyue.zhang@oss.qualcomm.com/ Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
🔨 Build Failure Analysis — PR #1611PR: #1611
VerdictThe build failed during automerge due to 2 pre-existing merge conflicts. However, the PR introduces a critical compilation error: duplicate definition of 📎 Detailed analysis: Full report |
🔨 Build Failure Analysis — PR #1611PR: #1611
VerdictThis is not a compilation failure. The build failed during the pre-build automerge/integration step due to merge conflicts between the PR branch and the baseline integration branch. Both conflicts are integration issues, not PR-introduced compilation errors. 📎 Detailed analysis: Full report |
PR #1611 — validate-patchPR: #1611
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PR #1611 — checker-log-analyzerPR: #1611
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The PCIe QMP PHYs on QCS8300 and SA8775p require dedicated qref and refgen voltage supplies for stable operation. Without enabling these supplies, PCIe may be unstable and the system can occasionally crash under certain scenarios.
The refgen supply works around a hardware issue where both QREF and the PCIe PHY are expected to depend on refgen2, but QREF actually depends on refgen3. This series therefore votes for refgen3 manually via the refgen supply.
Change 1: phy: qcom: qmp-pcie: Add qref and refgen regulator vote for QCS8300 and SA8775p PHY
Change 2: arm64: dts: qcom: qcs8300: Add qref and refgen supply for PCIe PHYs
Change 3: arm64: dts: qcom: sa8775p: Add qref and refgen supply for PCIe PHYs
This patch series is currently under internal review and will be submitted to the upstream Linux kernel community.
Link: http://shc-kerarch-hyd:8080/kernel_archive/20260703094224.990231-1-ziyue.zhang@oss.qualcomm.com/
CRs-Fixed: