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chore: Split serializer from PHY - #34

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split-axi-serializer
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chore: Split serializer from PHY#34
Lore0599 wants to merge 5 commits into
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split-axi-serializer

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@Lore0599 Lore0599 commented Aug 6, 2026

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Split serializer from PHY

This PR introduces an intermediate module, slink_serializer, which handles converting the AXI protocol into AXI-Stream and splitting the payload into packets.

This refactor enables the following:

  • The protocol/control-flow logic can be reused with different PHY implementations (e.g., UCIe).
  • Moving slink_reg out of the serializer allows multiple serializers (and eventually serial links) to be instantiated in the same design, each with its own parametrization. This isn't currently possible: once a downstream project depends on the serial link, IP parameters such as NumChannels, NumLanes, and EnDdr are inherited directly from the generated RDL, tying every instance to the same configuration.

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Lore0599 requested a review from fischeti as a code owner August 6, 2026 01:05
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Lore0599 requested review from fischeti and micprog and removed request for fischeti August 6, 2026 01:05
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Lore0599 marked this pull request as draft August 6, 2026 08:25
ricted98 and others added 4 commits August 7, 2026 00:15
Extract the Protocol Layer, Data Link Layer, Channel Allocator, and
config-register front-end of the serial link into a new
slink_serializer module, exposing a per-channel phy_data_t packet
stream (+ TX PHY clock-div/shift config) as its port boundary instead
of driving slink_phys_layer directly.

slink.sv becomes a thin wrapper pairing slink_serializer with the
existing slink_phys_layer generate loop, keeping its external port
list and module name unchanged for compatibility with slink_isolate
and downstream integrations (e.g. gwaihir).

This lets slink_serializer be reused standalone with a different
physical/transport backend in another project.

Verified: verible-verilog-lint clean; tb_axi_slink (default 1-channel,
no channel allocator) and tb_ch_calib_slink (regenerated at 4
channels, exercising the channel-allocator branch) both pass with 0
errors in vsim.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
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Lore0599 force-pushed the split-axi-serializer branch from 44ce78b to 927d84c Compare August 6, 2026 22:16
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The new phy_data_* interface in slink_serializer.sv reads as a symmetric valid/ready handshake in both directions, but on the reference PHY the RX-side ready carries no backpressure authority. In slink_phys_layer.sv the receive CDC (i_cdc_in) ties src_valid_i to 1'b1 and leaves src_ready_o unconnected (around lines 144-146), so words recovered off the wire are enqueued unconditionally; data_in_ready_i (the serializer's phy_data_in_ready_o) gates only the drain side. The CdcRxFifoFull overrun assertion that would flag this is commented out just below.

So backpressure is owned above the seam by the serializer's credit scheme, not by the PHY. credit_t travels in-band inside payload_t, and RecvFifoDepth = NumCredits * PayloadSplits sizes the receive path so credits, not wire-level ready, prevent overflow. Packet boundaries sit above the seam as well: the PHY sees only opaque fixed-width phy_data_t words with no framing, the data-link layer rebuilds a payload by counting PayloadSplits words, and multi-channel alignment leans on the channel allocator's cfg_rx_sync_en.

The implication for a different backend such as UCIe/RDI is that it must reproduce the same lossless, in-order, word-aligned, credit-bounded delivery, because the serializer carries no per-word framing to resync after a dropped or inserted word, and its RX ready is not a stall the way RDI's pl_trdy/valid semantics are. I have only read this repo at HEAD (911b32c); I have not seen the RDI adapter, so whether it closes that gap I cannot say from here.

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3 participants