ci: Lint the testbenches too and clear what that exposes

[DanielKellerM]

Stacked on #186 (which added the tree-scoped gate over src/); merge after it.

The style gate only ever walked src/, so test/ had never been linted and had accumulated 209 violations. This extends the gate to the testbenches and fixes what it reports, leaving the tree at zero.

The one change that is not cosmetic

tb_idma_otf_transpose.sv used $test$plusargs("BP"), which verible rejects. Swapping to $value$plusargs alone would have been a silent regression: idma.mk passed +BP with no value, so the parse would have failed, backpressure would have stayed 0, and the backpressured transpose stimulus would have become a byte-identical rerun of the first - verible quiet, suite green, one stimulus gone.

So the makefile and the testbench change together (+BP=1 plus $value$plusargs("BP=%d", ...)). Verified on the same binary:

./simv +BP=1  ->  [TB] case M=13 N=19 EB=1 ... BP=1
./simv +BP    ->  [TB] case M=13 N=19 EB=1 ... BP=0

and the two suite runs still differ (otf_transpose BP=0 vs otf_transpose_bp BP=1), so the second stimulus is genuinely live.

Other classes

Line length, trailing whitespace, tabs, explicit parameter and task-parameter types, constraint and parameter naming, unpacked dimension ordering. The task-lifetime changes in test/include/tb_tasks.svh are the ones with real semantics: those tasks contain no time control, so static storage is currently safe and automatic is identical, but it removes the hazard the day someone adds a @(posedge clk) to a memory task - that file backs all eight generated backend testbenches, and init_mem and compare_mem already run from different initial blocks.

Renaming constraint irq to irq_c also removes a name collision with the module-level logic irq in both desc64 testbenches.

One waiver, named and justified

interface-name-style on test/idma_intf.sv: IDMA_DV/IDMA_ND_DV are the exported verification API and are instantiated by name by downstream verification this repo's CI cannot see, so renaming them here would break it silently. No rule is disabled globally and no directory is excluded except the vendored files under test/future/, which are named explicitly.

Verified

• make idma_lint_sv over src/ and test/: 0 violations
• make idma_verify_all: rc=0, 24 elaboration OK, 21 sim PASS, 0 failures, 218 s
• Real Questa simulations exercising the shared task library: rw_axi, r_obi_w_axi and rw_obi all pass with their own per-variant configurations, gated on the transcript rather than the exit code

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