Rework PDK handling and add post-synthesis simulation

[phsauter]

• Technology handling: Reworked setup and changed to SG13CMOS5L as the main supported/default technology used in CI. The main change is that we now use the same technology/ directory as with DZ's cockpit and we also create symlinks to the PDK included here or downloaded on demand (GDS files). This should make future exercises and explanations significantly easier as for the user the flow and setup now looks identical.
• PDK: Liberty, LEF, and Verilog models are now copied into the repository instead of being pulled from a submodule. Patches in the verilog standard cells for compatibility with Verilator post-synthesis sim are required and added directly to the checked-in models as well as in patch files.
• Post-synthesis simulation: Added a new CI step that runs Verilator on a post-synthesis netlist with the full test suite. It reuses artifacts from synthesis (netlist) and RTL simulation (software binaries).
• Simulation robustness: Added checks for unknown/X values at the beginning of the JTAG operations, this makes debugging connectivity or testbench setup issues way easier.
• Backend flow: Updated technology-specific configurations for both metal stacks.
• Setup robustness: Improved handling of dangling technology links and made the setup flow more reproducible and self-checking.