Upgrade Cheshire (64-bit CVA6) by Xeratec · Pull Request #84 · pulp-platform/chimera

Xeratec · 2026-03-05T16:09:11Z

Upgrades the Cheshire host to a recent main-based version (64-bit CVA6) and rebases
Chimera onto the v0.2.0 template line. Chimera-specific Cheshire changes live on
wiesep/chimera-main.

Rebased onto pulp-platform/chimera:main; supersedes the earlier #82-based version.

The generic (non-Chimera) parts of the Cheshire changes — 32-bit/XLEN parametrization and
the SerialLink-disabled fix — are being upstreamed in pulp-platform/cheshire#287.
Once that merges, wiesep/chimera-main can be rebased on top of it.

Dependencies (`Bender.yml` / new `Bender.local`)

cheshire: pinned commit → wiesep/chimera-main branch
axi: colluca/axi multicast branch → pinned commit bd1abffc
common_cells: 1.39.0, overridden in Bender.local to the snitch branch (ca9d577f)
register_interface: 0.4.3 → 0.4.7
memory_island: pinned commit → main
hyperbus: aottaviano/nonfree branch → 0.0.9
Add Bender.local overrides (common_cells, axi); remove workspace.package_links

Changes

Switch host to 64-bit: CHS_XLEN=64, cv64a6_imafdchsclic_sv39_wb (was cv32a6_convolve)
Cheshire AxiDataWidth → 64; add MemIslRegionLength; 64-bit-aware fast preload
Connect HyperBus to the LLC AXI port and enable the Cheshire LLC
Fix CVA6 stall error; regenerate Snitch bootrom; fix HyperBus test
Sim: configurable CHIM_HYPERBUS_SDF_PATH, -suppress 8386

To-do

Sanity-check the Cheshire changes on wiesep/chimera-main
Confirm the cheshire commit hash is pinned before merge (currently a branch ref)
Rebase wiesep/chimera-main onto feat: parametrize Cheshire for 32-bit cores + SerialLink fix cheshire#287 once it lands

phsauter · 2026-06-03T12:15:38Z

At this point we might want to consider directly moving to the incoming version with CVA6 v3

Cleanup

Lore0599

Thank you very much, teh PR looks very good. I left some comments, for some of them I'm open to discussion.

Lore0599 · 2026-08-10T14:39:20Z

+    cfg.AxiExtNumSlv = ExtClusters + MemoryIsland;
+    cfg.AxiExtNumRules = ExtClusters + MemoryIsland;

-    cfg.AxiExtRegionIdx = {HyperbusIdx, MemIslandIdx, ClusterIdx};
-    cfg.AxiExtRegionStart = {HyperbusRegionStart, MemIslRegionStart, ClusterRegionStart};
-    cfg.AxiExtRegionEnd = {HyperbusRegionEnd, MemIslRegionEnd, ClusterRegionEnd};
+    cfg.AxiExtRegionIdx = {MemIslandIdx, ClusterIdx};
+    cfg.AxiExtRegionStart = {MemIslRegionStart, ClusterRegionStart};
+    cfg.AxiExtRegionEnd = {MemIslRegionEnd, ClusterRegionEnd};


If you want to access teh hyperbus manually (without using the LLC), do you still have a path to it?

Lore0599 · 2026-08-10T14:42:36Z

+  logic [ChimeraAxiLlcArWidth-1:0] hyper_ar_data;
  logic [              LogDepth:0] hyper_ar_wptr;
  logic [              LogDepth:0] hyper_ar_rptr;
-  logic [ChimeraAxiSlvAwWidth-1:0] hyper_aw_data;
+  logic [ChimeraAxiLlcAwWidth-1:0] hyper_aw_data;
  logic [              LogDepth:0] hyper_aw_wptr;
  logic [              LogDepth:0] hyper_aw_rptr;
-  logic [ ChimeraAxiSlvBWidth-1:0] hyper_b_data;
+  logic [ ChimeraAxiLlcBWidth-1:0] hyper_b_data;
  logic [              LogDepth:0] hyper_b_wptr;
  logic [              LogDepth:0] hyper_b_rptr;
-  logic [ ChimeraAxiSlvRWidth-1:0] hyper_r_data;
+  logic [ ChimeraAxiLlcRWidth-1:0] hyper_r_data;
  logic [              LogDepth:0] hyper_r_wptr;
  logic [              LogDepth:0] hyper_r_rptr;
-  logic [ ChimeraAxiSlvWWidth-1:0] hyper_w_data;
+  logic [ ChimeraAxiLlcWWidth-1:0] hyper_w_data;
  logic [              LogDepth:0] hyper_w_wptr;
  logic [              LogDepth:0] hyper_w_rptr;


I think all this could be replaced with teh axi typedefs: https://github.com/pulp-platform/axi/blob/4da15979747f326bde2f9869c64e587ce599772c/include/axi/typedef.svh#L134-L141

Lore0599 · 2026-08-10T15:06:40Z

-    .RstChipBase     (ChsCfg.LlcOutRegionStart),
-    .RstChipSpace    (HyperbusRegionEnd - HyperbusRegionStart),
+    .RstChipBase     (HyperbusRegionStart),
+    .RstChipSpace    (HypNumPhys * HypNumChips * 'h800_0000),


Two comments here:

You could write 'h800_0000 in a variable to make explicit where this parameter has been taken from?

Can we derive this parameter from those already defined in the chimera_pkg.sv? In this way we should have a single source of truth

Lore0599 · 2026-08-10T15:08:29Z

+    // setAllClusterReset(regPtr, 0);
+    // setAllClusterClockGating(regPtr, 0);


I suppose you commented this out since the test is not using any cluster.
If thsi is the case can we just remove the 2 code of lines?

Lore0599 · 2026-08-10T15:10:25Z

Is there a specific reason why we need the bender local?
I think it would be better to update teh Bender.lock (and YML)

Lore0599 · 2026-08-10T15:13:40Z

-    cfg.AxiDataWidth = 32;
+    cfg.AxiDataWidth = 64;
    cfg.AddrWidth = 48;
    cfg.LlcOutRegionEnd = 'hFFFF_FFFF;


Doesn't this line of code overwrite the previously changed line:
cfg.LlcOutRegionEnd = HyperbusRegionEnd;

Lore0599 · 2026-08-10T15:20:48Z

 VSIM_FLAGS_GUI = -voptargs=+acc

-override VSIM_FLAGS += -work $(VSIM_WORK)
+override VSIM_FLAGS += -work $(VSIM_WORK) -suppress 8386


Do we need to suppress this error? Why?

Lore0599 · 2026-08-10T15:23:51Z

-  snitch_cluster:           { git: "https://github.com/pulp-platform/snitch_cluster.git",     rev: 5b2fccd96c42812774c20ab2f9b811e164809789}
-  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.31.1}
+  register_interface:       { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.7 }
+  axi:                      { git: "https://github.com/colluca/axi",                          rev: bd1abffc0812f8170902e5fb93142c7785c0b8c1 } #


Not on you but one me: we should use versions and avoid referring to commits or branches.

Lore0599 · 2026-08-10T15:34:27Z

+  localparam int unsigned ChimeraAxiLlcIdWidth = ChsCfg.AxiMstIdWidth   +
+                                     $clog2(AxiIn.num_in)+
+                                     ChsCfg.LlcNotBypass    ;


To double-check, but I think you already have this parameter decalred at thetop in this macro:

`CHESHIRE_TYPEDEF_ALL(csh_, CheshireCfg)

you could do something like:
localparam int unsigned ChimeraAxiLlcIdWidth = $bits(axi_llc_id_t);

Lore0599 · 2026-08-10T15:40:37Z

+  localparam int unsigned ChimeraAxiLlcArWidth = (2**LogDepth)*
+                                      axi_pkg::ar_width(ChsCfg.AddrWidth   ,
+                                                        ChimeraAxiLlcIdWidth      ,
+                                                        ChsCfg.AxiUserWidth);
+  localparam int unsigned ChimeraAxiLlcAwWidth = (2**LogDepth)*
+                                        axi_pkg::aw_width(ChsCfg.AddrWidth  ,
+                                                        ChimeraAxiLlcIdWidth      ,
+                                                        ChsCfg.AxiUserWidth);
+  localparam int unsigned ChimeraAxiLlcBWidth  = (2**LogDepth)*
+                                        axi_pkg::b_width(ChimeraAxiLlcIdWidth     ,
+                                                        ChsCfg.AxiUserWidth);
+  localparam int unsigned ChimeraAxiLlcRWidth  = (2**LogDepth)*
+                                        axi_pkg::r_width(ChsCfg.AxiDataWidth,
+                                                        ChimeraAxiLlcIdWidth      ,
+                                                        ChsCfg.AxiUserWidth);
+  localparam int unsigned ChimeraAxiLlcWWidth  = (2**LogDepth)*
+                                        axi_pkg::w_width(ChsCfg.AxiDataWidth,
+                                                        ChsCfg.AxiUserWidth );
+


I think we could do the code slightly less verbose reusing the type already generate by teh CHESHIRE_TYPEDEF_ALL, something like:

Suggested change

localparam int unsigned ChimeraAxiLlcArWidth = (2**LogDepth)*

axi_pkg::ar_width(ChsCfg.AddrWidth ,

ChimeraAxiLlcIdWidth ,

ChsCfg.AxiUserWidth);

localparam int unsigned ChimeraAxiLlcAwWidth = (2**LogDepth)*

axi_pkg::aw_width(ChsCfg.AddrWidth ,

ChimeraAxiLlcIdWidth ,

ChsCfg.AxiUserWidth);

localparam int unsigned ChimeraAxiLlcBWidth = (2**LogDepth)*

axi_pkg::b_width(ChimeraAxiLlcIdWidth ,

ChsCfg.AxiUserWidth);

localparam int unsigned ChimeraAxiLlcRWidth = (2**LogDepth)*

axi_pkg::r_width(ChsCfg.AxiDataWidth,

ChimeraAxiLlcIdWidth ,

ChsCfg.AxiUserWidth);

localparam int unsigned ChimeraAxiLlcWWidth = (2**LogDepth)*

axi_pkg::w_width(ChsCfg.AxiDataWidth,

ChsCfg.AxiUserWidth );

localparam int unsigned ChimeraAxiLlcIdWidth = $bits(axi_llc_id_t);

localparam int unsigned ChimeraAxiLlcArWidth = (2 ** LogDepth) * $bits(axi_llc_ar_chan_t);

localparam int unsigned ChimeraAxiLlcAwWidth = (2 ** LogDepth) * $bits(axi_llc_aw_chan_t);

localparam int unsigned ChimeraAxiLlcBWidth = (2 ** LogDepth) * $bits(axi_llc_b_chan_t);

localparam int unsigned ChimeraAxiLlcRWidth = (2 ** LogDepth) * $bits(axi_llc_r_chan_t);

localparam int unsigned ChimeraAxiLlcWWidth = (2 ** LogDepth) * $bits(axi_llc_w_chan_t);

You can also add in include/typedef.sv after the memory island macro, one more macro to declare those types for you.

Xeratec requested a review from Lore0599 March 5, 2026 16:09

Xeratec self-assigned this Mar 5, 2026

Xeratec force-pushed the dev/64bit branch 2 times, most recently from 332d0e9 to f930a6c Compare March 10, 2026 15:49

Xeratec added 7 commits July 7, 2026 15:52

Fix Hyperbus test

b73aa13

Switch to 64-bit CVA6 (local Cheshire Version)

7de6e42

Cleanup

Fix CVA6 Stall error

3518ba7

Update Cheshire and regenerate Snitch Bootrom

9533591

Move Hyperbus to AXI LLC

1680f99

Enable LLC

0ff4dc1

Rebase to latest chimera template version

b9c65a7

Xeratec changed the base branch from devel to main July 16, 2026 13:32

Xeratec force-pushed the dev/64bit branch from 477836d to b9c65a7 Compare July 16, 2026 13:32

This was referenced Jul 16, 2026

feat: parametrize Cheshire for 32-bit cores + SerialLink fix pulp-platform/cheshire#287

Draft

Cleanup + SW verification framework (chimera-sdk) #90

Draft

rdl: generate SoC-control regs + memory map from SystemRDL #91

Draft

Lore0599 requested changes Aug 10, 2026

View reviewed changes

Lore0599 reviewed Aug 10, 2026

View reviewed changes

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Upgrade Cheshire (64-bit CVA6) - #84

Upgrade Cheshire (64-bit CVA6)#84
Xeratec wants to merge 7 commits into
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Xeratec:dev/64bit

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		// setAllClusterReset(regPtr, 0);
		// setAllClusterClockGating(regPtr, 0);

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Xeratec commented Mar 5, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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Dependencies (Bender.yml / new Bender.local)

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Xeratec commented Mar 5, 2026 •

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Dependencies (`Bender.yml` / new `Bender.local`)