Transistor-level design and simulation of a 1,024-bit (32×32) SRAM macro, built bottom-up in Cadence Virtuoso — from individual CMOS gates through the 6T bit-cell, up to the full array with its address path and read datapath.
DVD (Digital VLSI Design) Course Project — IIIT Hyderabad
📄 Full report: DVD_Project__Riyal_.pdf
SRAM retains data in bistable latching circuitry rather than by periodic refresh (as DRAM does), which buys speed and low latency at the cost of density and per-bit area. This project designs a 32×32 array — the building block that bridges elementary transistor-level cell design and complex multi-bank memory architectures.
The design is a complete memory macro, not just a cell array:
| Block | Role |
|---|---|
| 5-bit hybrid adder | Computes the target word address from array base + offset |
| 5:32 row decoder | Decodes the 5-bit address to assert exactly one Word Line |
| 32×32 6T cell array | 1,024 bit-cells, cross-coupled-inverter storage |
| Pre-charge circuit | Charges BL/BLB to VDD before each read |
| Sense amplifier | Resolves the small bit-line differential to full rail |
Supply: VDD = 0.9 V · Channel length: 30 nm · Operating frequency (for power analysis): 50 MHz
| Metric | Value |
|---|---|
| Full-circuit input→output delay | 78.3 ps |
| 5-bit adder critical path | 77.33 ps |
| 5:32 decoder worst-case delay | 27.8 ps |
| Sense amplifier delay | 126.5 ps |
| Sense amplifier sensitivity | 0.03 V |
| Rise / fall time | 18.91 ps / 13.2 ps |
| Static (leakage) power | 99.216 µW (Ileak = 110.24 µA) |
| Short-circuit power | 2.44 µW (Ipeak = 5.422 mA) |
| Dynamic power | 40.5 × 10⁶ · CL W |
Every gate was hand-sized against a minimum-sized inverter to minimize delay.
| Gate | Sizing (Wp / Wn) | Tplh | Tphl | Used in |
|---|---|---|---|---|
| Inverter | 2:1 p:n ratio | 17.61 ps | 32.21 ps | SRAM cell, load caps, precharge, decoder |
| AND | 300 nm / 300 nm | 28.4 ps | 41.6 ps | Adder generate logic (Gi) |
| OR | 600 nm / 150 nm | 43.1 ps | 34.2 ps | Adder final carry |
| XOR | 600 nm / 300 nm | — | — | Adder propagate logic (Pi) |
| 3-input NAND | 150 nm / 450 nm | 25.3 ps | 49.4 ps | Decoder pre-decoder |
| NOR | 600 nm / 150 nm | 35.3 ps | 27.2 ps | Decoder final stage |
The 2:1 PMOS:NMOS width ratio in the inverter equalizes pull-up and pull-down drive strength.
Three blocks in series: two 2-bit carry-lookahead adders + one 1-bit full adder.
P_i = A_i ⊕ B_i G_i = A_i · B_i C_(i+1) = P_i·C_i + G_i
Why hybrid rather than pure CLA or ripple-carry:
- vs. ripple-carry — far fewer sequential carry stages, so much lower delay.
- vs. a full 5-bit CLA — a 5-bit CLA needs 4- and 5-input AND gates, whose fan-in dominates the delay. The 2-2-1 split caps fan-in and avoids that penalty.
Critical path measured at 77.33 ps for A = 01111 (15) + B = 00001 (1) → Cout/S4.
Rather than 32 five-input AND gates, the decoder is split hierarchically:
Pre-decoder
- 4 × 3-input NAND producing
(A'·B')'through(A·B)'— the third input is Enable, folding enable logic into the pre-decode stage at no extra cost. - 8 × 3-input NAND producing
(C'·D'·E')'through(C·D·E)'.
Main decoder
- A grid of 32 two-input NOR gates. Row 0 takes
(A'B'En)and(C'D'E'); row 31 takes(A·B·En)and(C·D·E).
Splitting the decoder cuts input capacitance and final-stage fan-in, giving a worst-case decode of 27.8 ps (measured for ABCDE 00000 → 00001).
Two cross-coupled inverters (M3/M4 and M5/M6) form the storage latch; M1 and M2 are the access transistors gated by the Word Line.
Three modes
- Hold — WL low, access transistors off. The cell reduces to two cross-coupled inverters in positive feedback; no DC path from VDD to ground, so only leakage is drawn.
- Read — BL and BLB pre-charged to VDD, WL asserted. The node storing '0' sinks current from its bit line while the complementary line stays high; the sense amplifier resolves the resulting differential.
- Write — Bit lines driven to the new data, WL asserted. The strong external drivers overpower the weak internal PMOS pull-ups and flip the latch, which then reinforces the new state through positive feedback.
Sizing hierarchy — resolving the conflict between read stability and write ability:
| Transistors | Strength | Size | Reason |
|---|---|---|---|
| Pull-down (M4, M6) | Strongest | W = 300 nm, L = 30 nm | Must win the read-time voltage divider against the access transistor, preventing read upset |
| Access (M1, M2) | Medium | W = 150 nm, L = 30 nm | Weaker than pull-down (for reads), stronger than pull-up (for writes) |
| Pull-up (M3, M5) | Weakest | W = 150 nm, L = 30 nm | Must be overpowered by the access transistor during a write |
Pull-up and access transistors share a width, but the PMOS pull-ups remain weaker due to lower hole mobility. Widths were chosen large for speed; they can be scaled down for area without affecting functionality.
- SNM (Static Noise Margin) — read stability. Measured by breaking the cross-coupled feedback, sweeping a DC source on the half-cell's inverter gate from 0 to VDD, then mirroring and overlaying the plot to form the butterfly curve. SNM is the side of the largest square fitting inside the lobes.
- WNM (Write Noise Margin) — write ability, i.e. immunity to write failure when flipping the stored bit. Measured by breaking feedback and sweeping both inverter gates, plotting Q and QB.
Worst case observed: node Q settles at 138.368 mV rather than a true 0 V, because the pull-up PMOS keeps fighting the access NMOS — the residual voltage reflects the drive-strength ratio of the two.
A latching (cross-coupled inverter) sense amplifier — necessary because bit lines are long and heavily loaded, so swinging them full-rail would be slow and power-hungry. Instead the cell develops only ~50–200 mV of swing and the amplifier does the heavy lifting.
Three phases:
- Pre-charge & equalization — amplifier disabled, both bit lines equalized so ΔV = 0 (any offset here becomes an error).
- Signal development — WL asserted; the cell slightly discharges one bit line, creating VBL < VBLB.
- Amplification (latching) — SE asserted, cross-coupled positive feedback regenerates the small ΔV to full rail and latches it.
Delay was measured by stabilizing the amplifier at its metastable point with the eq signal, pre-charging the bit lines, then timing from enable to output: 126.5 ps. A parametrized sweep of bit-line-bar from 0.8 V to 0.89 V in 0.01 V steps gave correct output from 0.87 V onward → sensitivity 0.03 V.
- High-speed adder — the 2-2-1 architecture and careful ordering of inputs/intermediate signals minimizes the number of series transistors on the worst-case path.
- Optimized decoder — hierarchical pre-decoding reduces input capacitance and final-stage fan-in, improving transition times.
The final architecture integrates a robust 6T bit-cell array with optimized peripheral circuitry. The design's main strength is delay optimisation: the hybrid 2-2-1 CLA holds the adder critical path to 77.33 ps (avoiding ripple-carry latency), and pre-decoding yields a 27.8 ps decode time.
Future work: 8T or 10T bit-cell topologies would separate the read and write paths, potentially allowing lower supply voltages and higher noise immunity in larger arrays.
| Name | Roll No. |
|---|---|
| Pranav Shankar | 2023112011 |
| Aanchal Mundhada | 2023112016 |
| Krrish Goenka | 2023112023 |
| Sajiv Singh | 2023112003 |
| Prakhar Gupta | 2023112019 |
- A. Paul, M. Hasan, M. M. Azmir, and U. Irin, "Design and comparative analysis of an optimized 5x32 SRAM address decoder for high speed and high density applications at 22nm technology," Sept. 2025.
- J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, Prentice Hall, 2002, vol. 2.
- P. N. V. Kiran and N. Saxena, "Design and analysis of different types SRAM cell topologies," 2015 2nd International Conference on Electronics and Communication Systems (ICECS), 2015, pp. 1060–1065.