TensorRT 11 support (Blackwell / strongly-typed networks), incl. FP16

[gweber]

Summary

Makes the TensorRT backend build and run against TensorRT 11 (e.g. on Blackwell / sm_120/sm_121 with CUDA 13), including FP16. Currently the backend fails to compile against TRT 11, and TRT 10 doesn't support these GPUs — so there's no working TRT path on the newest NVIDIA hardware today. Related: #1041 (RTX 5090 / Blackwell).

The change is in two commits that tell the story: first the FP32 port (gets it compiling + correct), then FP16 restored.

Why

TensorRT 11 removes weakly-typed networks and the entire builder-driven mixed-precision mechanism this backend relied on: BuilderFlag::kFP16, IBuilder::platformHasFastFp16(), per-layer ILayer::setPrecision()/setOutputType(), ITensor::setType(), kOBEY/kPREFER_PRECISION_CONSTRAINTS, and the kEXPLICIT_BATCH network-creation flag are all gone. Every network is now strongly typed: a tensor's precision is whatever the network (or parsed ONNX graph) declares, and the builder will not silently insert reformats.

What changed

1. FP32 strongly-typed port (neuralnet/trtbackend.cpp, command/sandbox.cpp)

• createNetworkV2(0U) instead of the removed kEXPLICIT_BATCH flag.
• Drop the kFP16/precision-constraint flags, platformHasFastFp16(), the post-parse FP32 pin loop, and all setPrecision/setType calls (the graph carries its own types now).
• Outputs constrained to linear layout via setAllowedFormats only.

2. FP16 in the ONNX graph (neuralnet/onnxmodelbuilder.{cpp,h})
Under strongly-typed networks FP16 has to live in the graph, so OnnxModelBuilder gains a convertGraphToFloat16 post-pass: after the FP32 graph is built, every node is rewritten to FP16 except the numerically-sensitive regions — the RMSNorm square -> reduce -> sqrt reductions and the trunk tip + policy/value heads (exactly the node sets the old weakly-typed path pinned via setPrecision + kOBEY_PRECISION_CONSTRAINTS). Cast nodes are inserted in topological position on every FP16<->FP32 boundary edge, and FP16-only weight initializers are converted to FP16. Graph inputs/outputs stay FP32, so InputBuffers/getOutput and the device bindings are unchanged.

floatToHalf clamps finite out-of-range values to the max finite half (±65504) instead of promoting to Inf. KataGo uses a 1e9 sentinel as the off-board attention mask bias; an Inf there yields 0*Inf = NaN ("nonfinite policy sum") in the attention softmax. Clamping preserves the masking semantics (a huge finite negative bias still drives softmax to ~0) and matches onnxconverter-common.

tuneSalt bumped to invalidate FP16-pinned plan/timing caches from older builds.

Validation

Built on a GB10 (Grace-Blackwell, sm_121) with TensorRT 11.0 / CUDA 13. katago testgpuerror against an Eigen CPU reference, 2179 positions at 9x9, on both a convnet (g170 b10c128) and an nbt-transformer (b4c256 ... rsnh):

	FP32 vs ref (winrate err avg/max)	FP16 vs ref (avg/max)
convnet	0.031% / 0.39%	0.090% / 0.93%
nbt-transformer	0.029% / 0.40%	0.081% / 0.50%

FP32 errors are at the TF32-tactic level; FP16 errors are normal half-precision magnitude, no NaN. The analysis engine returns valid policy/value/ownership. FP16 is ~2.4x the FP32 nnEval throughput on the 256-channel transformer at 19x19.

Notes

• The hand-built ModelParser path (trtDisableOnnx) is ported too but is FP32-only; the default ONNX-emitter path supports FP16. useFP16=false forces a fully-FP32 engine.
• Build deps unchanged except that the TRT backend needs protobuf (already required by the ONNX-emitter path).