Pinned Loading

1. wifi-csi-sensing wifi-csi-sensing Public

   Camera-less human pose (12 keypoints) & location estimation from Wi-Fi CSI · ESP32 5-RX capture → Zynq PS preprocessing → INT8 CNN accelerator in PL (Verilog RTL, AXI, UVM)

   Python

2. apb-uvm-vip apb-uvm-vip Public

   UVM-based Verification IP (VIP) for the AMBA APB protocol

   SystemVerilog

3. FPGA-VGA-PhotoBooth-Project FPGA-VGA-PhotoBooth-Project Public

   A self-service four-cut photobooth built entirely on FPGA (Basys3). Captures photos, lets users edit them in real time (stickers, drawing, color picker), and streams the result over UART to a PC we…

   SystemVerilog

4. rv32i-singlecycle-cpu rv32i-singlecycle-cpu Public

   RV32I Single Cycle CPU designed in SystemVerilog

   SystemVerilog

5. spi-rtl-uvm-verification spi-rtl-uvm-verification Public

   UVM-based verification of a custom SPI protocol, scoreboard checking and functional coverage

   SystemVerilog

6. verilog-rtl-collection verilog-rtl-collection Public

   Collection of Verilog RTL designs built for digital design practice

   Verilog