EE student at Purdue passionate about Digital Design, DSP, RF, and embedded systems.
Highlights
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fpga-audio-effects
fpga-audio-effects PublicMy specific contributions and work on the Harmonicore FPGA project.
SystemVerilog
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socet-1-shot-clock-fork
socet-1-shot-clock-fork PublicForked from wadhwat/socet-1-shot-clock
SystemVerilog
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WiFi-Attenuation-Simulator
WiFi-Attenuation-Simulator PublicSimulates a WiFi router's signal through an area with obstacles of different materials.
Python
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