Module services api

CONTRIBUTING.md

@@ -124,7 +124,7 @@ Please include the SPDX tag near the top of any new files you create:
 Here is an example of a recommended file header template:
 
 ```dart
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // example.dart

benchmark/many_submodules_benchmark.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2024 Intel Corporation
+// Copyright (C) 2024-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // many_submodules_benchmark.dart
@@ -33,7 +33,7 @@ class ManySubmodulesBenchmark extends AsyncBenchmarkBase {
   Future<void> run() async {
     final dut = ManySubmodulesModule(Logic(), numSubModules: 10000);
     await dut.build();
-    dut.generateSynth();
+    SystemVerilogService(dut).output;
   }
 }
 

benchmark/wave_dump_benchmark.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // wave_dump_benchmark.dart
@@ -56,7 +56,7 @@ class WaveDumpBenchmark extends AsyncBenchmarkBase {
     _mod = _ModuleToDump(Logic(), _clk);
     await _mod.build();
 
-    WaveDumper(_mod, outputPath: _vcdTemporaryPath);
+    WaveformService(_mod, outputPath: _vcdTemporaryPath);
 
     await Simulator.run();
 

doc/tutorials/chapter_2/helper.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023-2025 Intel Corporation
+// Copyright (C) 2023-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // helper.dart
@@ -13,7 +13,8 @@ import 'package:rohd/rohd.dart';
 
 Future<void> displaySystemVerilog(Module mod) async {
   await mod.build();
-  print('\nYour System Verilog Equivalent Code: \n ${mod.generateSynth()}');
+  print('\nYour System Verilog Equivalent Code: \n '
+      '${SystemVerilogService(mod).output}');
 }
 
 class LogicInitialization extends Module {

doc/tutorials/chapter_3/answers/exercise_sv.dart

@@ -33,7 +33,7 @@ void main() async {
   await fSub.build();
 
   // ignore: avoid_print
-  print(fSub.generateSynth());
+  print(SystemVerilogService(fSub).output);
 
   test('should return 0 when a and b equal 1', () async {
     a.put(1);

doc/tutorials/chapter_3/full_adder.dart

@@ -77,5 +77,5 @@ void main() async {
   final mod = FullAdderModule(a, b, cIn, faOps);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(SystemVerilogService(mod).output);
 }

doc/tutorials/chapter_4/answers/exercise_1_sv.dart

@@ -10,7 +10,7 @@ void main() async {
   final mod = NBitAdder(a, b);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(SystemVerilogService(mod).output);
 
   test('should return 255 when both inputs are added', () {
     a.put(127);

doc/tutorials/chapter_4/answers/exercise_2_sv.dart

@@ -9,7 +9,7 @@ void main() async {
 
   final mod = NBitSubtractor(a, b);
   await mod.build();
-  print(mod.generateSynth());
+  print(SystemVerilogService(mod).output);
 
   test('should return 5 when a is 25 and b is 20', () {
     a.put(25);

doc/tutorials/chapter_4/basic_generation_sv.dart

@@ -78,7 +78,7 @@ void main() async {
 
   await nbitAdder.build();
 
-  print(nbitAdder.generateSynth());
+  print(SystemVerilogService(nbitAdder).output);
 
   test('should return 10 when both inputs are 5.', () async {
     a.put(5);

doc/tutorials/chapter_5/answers/full_adder.dart

@@ -49,7 +49,7 @@ void main() async {
   final mod = FullAdder(a: a, b: b, carryIn: cIn);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(SystemVerilogService(mod).output);
 
   test('should return true if result sum similar to truth table.', () async {
     for (var i = 0; i <= 1; i++) {

doc/tutorials/chapter_5/answers/full_subtractor.dart

@@ -44,7 +44,7 @@ Future<void> main() async {
 
   await diff.build();
 
-  print(diff.generateSynth());
+  print(SystemVerilogService(diff).output);
 
   test('should return true if results matched truth table', () async {
     for (var i = 0; i <= 1; i++) {

doc/tutorials/chapter_5/answers/n_bit_subtractor.dart

@@ -36,7 +36,7 @@ Future<void> main() async {
   final mod = NBitFullSubtractor(a, b);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(SystemVerilogService(mod).output);
 
   test('should return 1 when a is 8 and b is 7.', () {
     a.put(8);

doc/tutorials/chapter_5/n_bit_adder.dart

@@ -79,7 +79,7 @@ void main() async {
 
   await nbitAdder.build();
 
-  // print(nbitAdder.generateSynth());
+  // print(SystemVerilogService(nbitAdder).output);
 
   test('should return 20 when A and B perform add.', () async {
     a.put(15);

doc/tutorials/chapter_7/answers/exercise_1_d_flip_flop.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023-2024 Intel Corporation
+// Copyright (C) 2023-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // exercise_1_d_flip_flop.dart
@@ -44,7 +44,7 @@ Future<void> main() async {
     final dff = DFlipFlop(data, reset, clk);
     await dff.build();
 
-    print(dff.generateSynth());
+    print(SystemVerilogService(dff).output);
 
     data.inject(1);
     reset.inject(1);
@@ -60,7 +60,7 @@ Future<void> main() async {
 
     unawaited(Simulator.run());
 
-    WaveDumper(dff,
+    WaveformService(dff,
         outputPath: 'doc/tutorials/chapter_7/answers/d_flip_flop.vcd');
 
     printFlop('Before');

doc/tutorials/chapter_7/shift_register.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023-2024 Intel Corporation
+// Copyright (C) 2023-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // shift_register.dart
@@ -69,7 +69,7 @@ void main() async {
     // kick-off the simulator, but we don't want to wait
     unawaited(Simulator.run());
 
-    WaveDumper(shiftReg,
+    WaveformService(shiftReg,
         outputPath: 'doc/tutorials/chapter_7/shift_register.vcd');
 
     printFlop('Before');

doc/tutorials/chapter_8/answers/exercise_1_spi.dart

@@ -139,7 +139,7 @@ void main() async {
 
   await tb.build();
 
-  print(tb.generateSynth());
+  print(SystemVerilogService(tb).output);
 
   testInterface.cs.inject(0);
   testInterface.sdi.inject(0);
@@ -163,7 +163,7 @@ void main() async {
   Simulator.setMaxSimTime(100);
   unawaited(Simulator.run());
 
-  WaveDumper(peri, outputPath: 'doc/tutorials/chapter_8/spi-new.vcd');
+  WaveformService(peri, outputPath: 'doc/tutorials/chapter_8/spi-new.vcd');
 
   await drive(LogicValue.ofString('01010101'));
 }

doc/tutorials/chapter_8/answers/exercise_2_toycapsule_fsm.dart

@@ -49,13 +49,13 @@ Future<void> main(List<String> args) async {
   final toyCap = ToyCapsuleFSM(clk, reset, dispenseBtn, coin);
   await toyCap.build();
 
-  print(toyCap.generateSynth());
+  print(SystemVerilogService(toyCap).output);
 
   toyCap.toyCapsuleStateMachine.generateDiagram();
 
   reset.inject(1);
 
-  WaveDumper(toyCap, outputPath: 'toyCapsuleFSM.vcd');
+  WaveformService(toyCap, outputPath: 'toyCapsuleFSM.vcd');
 
   Simulator.setMaxSimTime(100);
   Simulator.registerAction(25, () {

doc/tutorials/chapter_8/answers/exercise_3_pipeline.dart

@@ -34,14 +34,14 @@ void main(List<String> args) async {
     final pipe = Pipeline4Stages(clk, reset, a);
     await pipe.build();
 
-    // print(pipe.generateSynth());
+    // print(SystemVerilogService(pipe).output);
 
     a.inject(5);
     reset.inject(1);
 
     Simulator.registerAction(10, () => reset.put(0));
 
-    WaveDumper(pipe, outputPath: 'answer_1.vcd');
+    WaveformService(pipe, outputPath: 'answer_1.vcd');
 
     Simulator.registerAction(50, () async {
       // stage 4 / result: 30 + (30 * 3) = 120

doc/tutorials/chapter_8/carry_save_multiplier.dart

@@ -108,7 +108,7 @@ void main() async {
   reset.inject(1);
 
   // Attach a waveform dumper so we can see what happens.
-  WaveDumper(csm, outputPath: 'csm.vcd');
+  WaveformService(csm, outputPath: 'csm.vcd');
 
   Simulator.registerAction(10, () {
     reset.inject(0);

doc/tutorials/chapter_8/counter_interface.dart

@@ -63,9 +63,9 @@ Future<void> main() async {
 
   await counter.build();
 
-  print(counter.generateSynth());
+  print(SystemVerilogService(counter).output);
 
-  WaveDumper(counter,
+  WaveformService(counter,
       outputPath: 'doc/tutorials/chapter_8/counter_interface.vcd');
   Simulator.registerAction(25, () {
     intf.en.put(1);

doc/tutorials/chapter_8/oven_fsm.dart

@@ -192,7 +192,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Attach a waveform dumper so we can see what happens.
   if (!noPrint) {
-    WaveDumper(oven, outputPath: 'doc/tutorials/chapter_8/oven.vcd');
+    WaveformService(oven, outputPath: 'doc/tutorials/chapter_8/oven.vcd');
   }
 
   if (!noPrint) {

doc/tutorials/chapter_9/rohd_vf_example/lib/rohd_vf_example.dart

@@ -315,7 +315,7 @@ Future<void> main({Level loggerLevel = Level.FINER}) async {
   await tb.counter.build();
 
   // dump wave here
-  WaveDumper(tb.counter);
+  WaveformService(tb.counter);
 
   // Set a maximum simulation time so it doesn't run forever
   Simulator.setMaxSimTime(300);

example/example.dart

@@ -61,7 +61,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Let's see what this module looks like as SystemVerilog, so we can pass it
   // to other tools.
-  final systemVerilogCode = counter.generateSynth();
+  final systemVerilogCode = SystemVerilogService(counter).output;
   if (!noPrint) {
     print(systemVerilogCode);
   }
@@ -70,7 +70,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Attach a waveform dumper so we can see what happens.
   if (!noPrint) {
-    WaveDumper(counter);
+    WaveformService(counter);
   }
 
   // Let's also print a message every time the value on the counter changes,

example/fir_filter.dart

@@ -96,7 +96,7 @@ Future<void> main({bool noPrint = false}) async {
   await firFilter.build();
 
   // Generate SystemVerilog code.
-  final systemVerilogCode = firFilter.generateSynth();
+  final systemVerilogCode = SystemVerilogService(firFilter).output;
   if (!noPrint) {
     // Print SystemVerilog code to console.
     print(systemVerilogCode);
@@ -108,7 +108,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Attach a waveform dumper.
   if (!noPrint) {
-    WaveDumper(firFilter);
+    WaveformService(firFilter);
   }
 
   // Let's set the initial setting.

example/logic_array.dart

@@ -58,14 +58,14 @@ Future<void> main({bool noPrint = false}) async {
   // Build the module
   await logicArrayExample.build();
 
-  final systemVerilogCode = logicArrayExample.generateSynth();
+  final systemVerilogCode = SystemVerilogService(logicArrayExample).output;
   if (!noPrint) {
     print(systemVerilogCode);
   }
 
   // Simulate the module
   if (!noPrint) {
-    WaveDumper(logicArrayExample);
+    WaveformService(logicArrayExample);
   }
 
   // Set the input values

example/oven_fsm.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023-2024 Intel Corporation
+// Copyright (C) 2023-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // oven_fsm.dart
@@ -225,7 +225,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Attach a waveform dumper so we can see what happens.
   if (!noPrint) {
-    WaveDumper(oven, outputPath: 'oven.vcd');
+    WaveformService(oven, outputPath: 'oven.vcd');
   }
 
   // Kick off the simulation.

example/tree.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // tree.dart
@@ -85,7 +85,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Below will generate an output of the ROHD-generated SystemVerilog:
   await tree.build();
-  final generatedSystemVerilog = tree.generateSynth();
+  final generatedSystemVerilog = SystemVerilogService(tree).output;
   if (!noPrint) {
     print(generatedSystemVerilog);
   }

lib/rohd.dart

@@ -1,6 +1,13 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
+//
+// rohd.dart
+// Main public API exports for the ROHD framework.
+//
+// 2026 July
+// Author: ROHD Contributors
 
+export 'src/diagnostics/diagnostics.dart';
 export 'src/exceptions/exceptions.dart';
 export 'src/external.dart';
 export 'src/finite_state_machine.dart';
@@ -12,6 +19,7 @@ export 'src/signals/signals.dart';
 export 'src/simulator.dart';
 export 'src/swizzle.dart';
 export 'src/synthesizers/synthesizers.dart';
+export 'src/synthesizers/systemverilog/system_verilog_service.dart';
 export 'src/utilities/naming.dart';
 export 'src/values/values.dart';
 export 'src/wave_dumper.dart';

lib/src/diagnostics/diagnostics.dart

@@ -0,0 +1,12 @@
+// Copyright (C) 2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// diagnostics.dart
+// Barrel export for the diagnostics library.
+//
+// 2026 July 16
+// Author: Desmond Kirkpatrick <desmond.a.kirkpatrick@intel.com>
+
+export 'module_service.dart';
+export 'module_services.dart';
+export 'waveform_service.dart';