fix(gen-verilog): tuple literal elements and destructure regs are width-cast - #1973
Merged
Conversation
…th-cast Refs #1948 Two tuple-in-Verilog width defects kept several specs red under icarus: - A tuple return literal `(1, true)` packed each element through gen_verilog_expr, which emits a bare unsized literal -- iverilog rejects an unsized operand in a concatenation ("operand has indefinite width"). Each element is width-cast to its declared tuple-element type now. - Tuple-DESTRUCTURE binding regs (`(a,b,c,d) = mesh_ip(1)`) were each declared 64-bit, so `{d,c,b,a} = <32-bit packed return>` sliced the value wrongly and every element read garbage. Each element reg is declared at its element width, taken from the callee's return tuple type. tri-net corpus: icarus 88 -> 94 (fpga_synthesis_report, hello, integration_tests, lite_crypto, mesh_routing, packet_loss_injection). bridge.v regenerated; unit suite at the single pre-existing red. FROZEN_HASH resealed. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
gHashTag
enabled auto-merge (squash)
August 8, 2026 20:29
Contributor
Contributor
|
📓 NotebookLM Notebook linked to this PR
This notebook contains session context, decisions, and artifacts for this work. |
gHashTag
added a commit
that referenced
this pull request
Aug 8, 2026
…1975) * test(gen-verilog): tuple contract expects width-cast concat operands Follow-up to #1973: tuple literal elements are now width-cast (`{32'((a-b)), 32'((a+b))}`) so iverilog accepts them in a concatenation; the phase40 contract test's exact-string expectation is updated to match. Auto-merge landed #1973 on the green required checks before the unit suite (not a required check) was consulted. Unit suite back to the single pre-existing red (bitnet_layer). FROZEN_HASH resealed. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> * docs: NOW entry for the tuple contract test update Refs #1948 Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> --------- Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
gHashTag
added a commit
that referenced
this pull request
Aug 8, 2026
Refs #1948 Follow-up to #1973: tuple literal elements are width-cast so iverilog accepts them in a concatenation; the phase40 contract test's exact-string expectation is updated. Auto-merge landed #1973 on green required checks before the unit suite (not a required check) was consulted. Unit suite back to the single pre-existing red. FROZEN_HASH resealed; NOW.md entries added. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Refs #1948
Two tuple-in-Verilog width defects:
(1, true)packed each element via gen_verilog_expr → bare unsized literal, rejected in the concatenation ("operand has indefinite width"). Elements are width-cast to their tuple-element type now.(a,b,c,d) = mesh_ip(1)) were declared 64-bit each, so{d,c,b,a} = <32-bit packed return>sliced wrongly. Each element reg declared at its element width from the callee's return tuple type.tri-net corpus: icarus 88 → 94 (fpga_synthesis_report, hello, integration_tests, lite_crypto, mesh_routing, packet_loss_injection). bridge.v regenerated; unit suite at the single pre-existing red. FROZEN_HASH resealed; NOW.md entries added.
🤖 Generated with Claude Code