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docs: write/control hardening also fails -> the seed-lottery is a GLOBAL clock/placement effect (Refs #1764) - #1906

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docs: write/control hardening also fails -> the seed-lottery is a GLOBAL clock/placement effect (Refs #1764)#1906
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Tests the last local hypothesis for the seed-lottery and concludes the root-cause arc.

Registered the destination index di and the result into flip-flops and wrote the register file from the registered address+data (a clean synchronous write) — bit-exact in simulation. On the AX7203 across eight seeds: several dead-routed, and every seed that responded still glitched (explode to ~1e16 or collapse to zero), same as the baseline.

Conclusion of the root-cause arc (cycles 82–100): every local register-based fix has failed — the combinational datapath at the endpoints (cycle 97), mid-cloud core pipeline (cycle 99), and the write/control path (now) were each resynchronised with flip-flops and none changed the lottery. A fault that survives registering every local logic boundary is, by elimination, a global effect: clock-distribution skew on the fabric IBUFDS net across a large --timing-allow-fail placement, routing, or IR-drop — not a logic hazard any local RTL edit can reach.

The practical answer stays seed-search (XOR trains bit-exact on a good seed). The remaining structural levers are a real clock tree (MMCM, buildable on this flow) which reduces skew, or commercial P&R timing closure. Added ruled-out item #11.

Board restored to the generated capstone (XOR 4/4). Docs-only. Refs #1764

…ffect (Refs #1764)

Registered the destination index di + result and wrote the rf from the
registered address+data (clean synchronous write); bit-exact in sim. On the
AX7203 across 8 seeds, several dead-routed and every responder still glitched,
same as baseline. Concludes the root-cause arc: every local register-based fix
(datapath endpoints cycle 97, mid-cloud cores cycle 99, write/control now) has
failed, so by elimination the seed-lottery is a global effect -- clock skew on
the fabric IBUFDS net across a large --timing-allow-fail placement, routing, or
IR-drop -- not a local logic hazard. Practical answer stays seed-search;
structural levers are a real clock tree (MMCM) or commercial P&R. Added
ruled-out #11.

Refs #1764

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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PR Dashboard

Generated at: 2026-08-07 20:45:45 UTC

Summary

Status Count
Total Open PRs 14
PRs with Failing Checks 1
PRs with All Checks Green 13
READY 5
FAILING 1
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=2bd87d0d139e != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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gHashTag merged commit 2f03496 into master Aug 7, 2026
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gHashTag deleted the docs/write-control-also-fails-global-effect branch August 7, 2026 20:47
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