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docs: pipeline prototype bit-exact, but dropped-in register won't cut depth -> go spec-level on_clock (Refs #1764) - #1904

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docs: pipeline prototype bit-exact, but dropped-in register won't cut depth -> go spec-level on_clock (Refs #1764)#1904
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Starts Variant 1 (pipeline the shared core) with an RTL prototype and reports what it revealed.

  • Auto-retiming ruled out. synth_xilinx -retime moves only a few levels (ltp 57 → 51 on GftSadd with two output registers) — not enough to split the deep cloud.
  • Two 2-stage GftSmul prototypes, both bit-exact. Cut after the product, and cut mid-RNE (after carry/q/r); each verified bit-exact to the combinational core over ~40 k random operands. But ltp rose 44 → 49 / 50: dropping a register into the generated combinational function defeats yosys's cross-function optimization of the inlined sadd/magmul/mul_noop, and the RNE-normalize/accumulator depth does not split at a hand-inserted register.
  • Implication: the pipeline must be a spec-level on_clock where t27c co-optimizes the stages (and the multiply becomes a real pipelined primitive), not a register hand-dropped into codegen output. Added as ruled-out items [TASK-001]: Fix graph.tri — add missing spec declarations, fix typo #8 (auto-retime) and feat(ring-1): lex all 28 specs without errors [SEED-1] #9 (dropped-in register).
  • Depth reduction is secondary anyway — the untested lever is mid-cloud resynchronization; since the microsequencer already waits settle ≫ 1 cycle, a latency-1 pipelined core needs no sequencer change, so the decisive next experiment is to build the trainer on pipelined cores and see if the glitch dies.

Prototypes in scratchpad/retime/. Board untouched (generated capstone, XOR 4/4). Docs-only. Refs #1764

…t depth (Refs #1764)

Variant 1 RTL prototype. Ruled out yosys auto-retiming (57->51, too weak).
Built two 2-stage GftSmul prototypes (cut after product; cut mid-RNE), both
bit-exact to the combinational core over ~40k random operands, but ltp rose
44->49/50: a register dropped into the generated combinational function
defeats yosys cross-function optimization and the RNE/accumulator depth does
not split there. Implication: the pipeline must be a spec-level on_clock where
the compiler co-optimizes stages (multiply becomes a real pipelined
primitive), not a hand-inserted register. Depth reduction is secondary anyway
-- the untested lever is mid-cloud resync, and since the microsequencer waits
settle >> 1 a latency-1 core needs no sequencer change. Added ruled-out items
#8 (auto-retime) and #9 (dropped-in register).

Refs #1764

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Generated at: 2026-08-07 20:08:36 UTC

Summary

Status Count
Total Open PRs 14
PRs with Failing Checks 1
PRs with All Checks Green 13
READY 5
FAILING 1
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=2bd87d0d139e != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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gHashTag merged commit 7efd441 into master Aug 7, 2026
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gHashTag deleted the docs/pipeline-proto-depth-blocked-by-codegen branch August 7, 2026 20:09
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