docs: a slower clock can't fix the seed-lottery — pipelining is the fix (Refs #1764) - #1897
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…ix (Refs #1764) Ruled out the "slow the deep path" remedy on two independent grounds: (a) a fabric-counter divided clock is unbuildable on openXC7 — nextpnr-xilinx cannot place a BUFG or BUFR driven from fabric (only clock-capable-pin / CMT sources), so only an MMCM/PLL could make a real divided clock; (b) even if built, it only adds settle time, and more settle does not cure the glitch (silicon is non-monotonic in settle — /128 worse than /64). Also re-confirmed create_clock on clk_p does not propagate through IBUFDS (internal net defaults to a loose 12 MHz and always "passes", so --timing-allow-fail was a no-op). Conclusion: the only viable structural fix is to PIPELINE the shared GftSmul/GftSadd (spec-level on_clock), which breaks the deep combinational hazard and is the prerequisite for training nets larger than XOR on this flow. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Investigated and ruled out the intuitive "run the deep shared-core path on a slower clock" remedy for the on-silicon seed-lottery marginality, on two independent grounds:
BUFGandBUFRfed by a divider bit fail with "Unable to find legal placement" (7-series clock-buffer inputs come from clock-capable pins / the CMT, not general routing). Only an MMCM/PLL could synthesize a real divided clock.settlegives the same real settle window (~µs) as the working/Nclock-enable, and more settle does not cure the glitch — silicon behaviour is non-monotonic in settle (/128glitched worse than/64, cycle 93). The fault is a placement hazard, not a settle shortage.Also re-confirmed
create_clockonclk_pdoes not propagate throughIBUFDS(internal net defaults to a loose 12 MHz target and always "passes", so--timing-allow-failwas effectively a no-op).Conclusion (re-prioritises the roadmap): the one viable structural fix is to PIPELINE the shared
GftSmul/GftSadd(a spec-levelon_clockpipelined multiply/add), which breaks the deep combinational hazard and is the prerequisite for on-silicon training beyond XOR (seed-search runs out at 62 steps).Docs-only; no code or gate changes. Refs #1764