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docs: a slower clock can't fix the seed-lottery — pipelining is the fix (Refs #1764) - #1897

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docs: a slower clock can't fix the seed-lottery — pipelining is the fix (Refs #1764)#1897
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Investigated and ruled out the intuitive "run the deep shared-core path on a slower clock" remedy for the on-silicon seed-lottery marginality, on two independent grounds:

  • Not buildable on openXC7. A fabric-counter divided clock needs a clock buffer, and nextpnr-xilinx cannot place one driven from fabric — both BUFG and BUFR fed by a divider bit fail with "Unable to find legal placement" (7-series clock-buffer inputs come from clock-capable pins / the CMT, not general routing). Only an MMCM/PLL could synthesize a real divided clock.
  • Wouldn't help even if built. A divided clock with the same microcode settle gives the same real settle window (~µs) as the working /N clock-enable, and more settle does not cure the glitch — silicon behaviour is non-monotonic in settle (/128 glitched worse than /64, cycle 93). The fault is a placement hazard, not a settle shortage.

Also re-confirmed create_clock on clk_p does not propagate through IBUFDS (internal net defaults to a loose 12 MHz target and always "passes", so --timing-allow-fail was effectively a no-op).

Conclusion (re-prioritises the roadmap): the one viable structural fix is to PIPELINE the shared GftSmul/GftSadd (a spec-level on_clock pipelined multiply/add), which breaks the deep combinational hazard and is the prerequisite for on-silicon training beyond XOR (seed-search runs out at 62 steps).

Docs-only; no code or gate changes. Refs #1764

…ix (Refs #1764)

Ruled out the "slow the deep path" remedy on two independent grounds:
(a) a fabric-counter divided clock is unbuildable on openXC7 — nextpnr-xilinx
cannot place a BUFG or BUFR driven from fabric (only clock-capable-pin / CMT
sources), so only an MMCM/PLL could make a real divided clock; (b) even if
built, it only adds settle time, and more settle does not cure the glitch
(silicon is non-monotonic in settle — /128 worse than /64). Also re-confirmed
create_clock on clk_p does not propagate through IBUFDS (internal net defaults
to a loose 12 MHz and always "passes", so --timing-allow-fail was a no-op).
Conclusion: the only viable structural fix is to PIPELINE the shared
GftSmul/GftSadd (spec-level on_clock), which breaks the deep combinational
hazard and is the prerequisite for training nets larger than XOR on this flow.

Refs #1764

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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PR Dashboard

Generated at: 2026-08-07 19:29:25 UTC

Summary

Status Count
Total Open PRs 13
PRs with Failing Checks 1
PRs with All Checks Green 12
READY 5
FAILING 1
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=f74459fc23c3 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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gHashTag merged commit 3683604 into master Aug 7, 2026
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gHashTag deleted the docs/slowclock-blocked-pipeline-is-fix branch August 7, 2026 19:30
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