docs: seed-lottery marginality is placement-level (Heisenbug evidence) - #1895
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…register bug On-chip observability attempt (widen the UART dump to expose hidden pre-activations z0/z1 next to y) changed the design from marginally-computing to all-zero output: the added probe re-placed the shared core past its unconstrained timing edge. Documents this Heisenbug as positive evidence that the fault is a timing/placement property of the whole deep path, not a localizable microcode step. Fix remains a real multicycle constraint (commercial P&R), not a code change. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-08-07 19:12:23 UTC
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Superseded by a single-commit PR with per-commit issue reference (L1 traceability). |
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Records a measured negative result from the on-silicon training work: an attempt at on-chip observability (widening the UART result dump to expose the hidden pre-activations z0/z1 alongside the output y) flipped the design from marginally-computing to all-zero output. The extra logic re-placed the shared core past its (unconstrained) timing edge — a genuine Heisenbug that is itself evidence the seed-lottery fault is a placement/timing property of the whole deep combinational path, not a localizable single-register bug. The remedy is a real multicycle timing constraint (commercial P&R), not an RTL change.
Docs-only; no code or gate changes. Refs #1764