Skip to content

test: synth gate asserts zero transparent latches in the netlist - #1893

Merged
gHashTag merged 1 commit into
masterfrom
test/synth-zero-latch-guard
Aug 7, 2026
Merged

test: synth gate asserts zero transparent latches in the netlist#1893
gHashTag merged 1 commit into
masterfrom
test/synth-zero-latch-guard

Conversation

@gHashTag

@gHashTag gHashTag commented Aug 7, 2026

Copy link
Copy Markdown
Owner

Motivated by a root-cause hunt for the on-silicon seed-lottery marginality. Finding: the gen-verilog GF-T cores (GftSmul/GftSadd) infer dozens of latches during yosys proc (function locals conditionally assigned), but synth_xilinx optimizes them all away → 0 latch cells in the final netlist. So latches are not the marginality cause here (nor setup, nor hold — all three hypotheses killed board-independently). But a latch that survived synthesis would be a level-sensitive / placement-sensitive silicon-reliability hazard that iverilog verification never catches.

Added a permanent guard: the synth phase now asserts 0 transparent latch cells (LD*/*LATCH*) in the synthesized netlist and reports '0 latches' per topology. Passes today; catches a future gen-verilog regression that leaves a real latch on silicon. Still ALL SYNTHESIZE. Refs #1764

Motivated by a root-cause hunt for the on-silicon seed-lottery marginality. Finding:
the gen-verilog GF-T cores infer dozens of latches during yosys proc (function locals
conditionally assigned), but synth_xilinx optimizes them all away -> 0 latch cells in
the final netlist. So latches are NOT the marginality cause here (nor setup nor hold --
all three killed board-independently). But a latch that survived synthesis would be a
level-sensitive/placement-sensitive silicon-reliability hazard iverilog verification
never catches. The synth phase now asserts 0 transparent latch cells (LD*/*LATCH*) and
reports '0 latches' per topology -- passes today, catches a future gen-verilog
regression that leaves a real latch on silicon.

Refs #1764

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@github-actions

github-actions Bot commented Aug 7, 2026

Copy link
Copy Markdown
Contributor

PR Dashboard

Generated at: 2026-08-07 18:50:47 UTC

Summary

Status Count
Total Open PRs 13
PRs with Failing Checks 1
PRs with All Checks Green 12
READY 5
FAILING 1
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=f74459fc23c3 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@github-actions

github-actions Bot commented Aug 7, 2026

Copy link
Copy Markdown
Contributor

📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

@gHashTag
gHashTag merged commit 8f43193 into master Aug 7, 2026
18 checks passed
@gHashTag
gHashTag deleted the test/synth-zero-latch-guard branch August 7, 2026 18:56
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant