test: synth gate asserts zero transparent latches in the netlist - #1893
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Motivated by a root-cause hunt for the on-silicon seed-lottery marginality. Finding: the gen-verilog GF-T cores infer dozens of latches during yosys proc (function locals conditionally assigned), but synth_xilinx optimizes them all away -> 0 latch cells in the final netlist. So latches are NOT the marginality cause here (nor setup nor hold -- all three killed board-independently). But a latch that survived synthesis would be a level-sensitive/placement-sensitive silicon-reliability hazard iverilog verification never catches. The synth phase now asserts 0 transparent latch cells (LD*/*LATCH*) and reports '0 latches' per topology -- passes today, catches a future gen-verilog regression that leaves a real latch on silicon. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Motivated by a root-cause hunt for the on-silicon seed-lottery marginality. Finding: the gen-verilog GF-T cores (GftSmul/GftSadd) infer dozens of latches during yosys
proc(function locals conditionally assigned), butsynth_xilinxoptimizes them all away → 0 latch cells in the final netlist. So latches are not the marginality cause here (nor setup, nor hold — all three hypotheses killed board-independently). But a latch that survived synthesis would be a level-sensitive / placement-sensitive silicon-reliability hazard that iverilog verification never catches.Added a permanent guard: the synth phase now asserts 0 transparent latch cells (
LD*/*LATCH*) in the synthesized netlist and reports '0 latches' per topology. Passes today; catches a future gen-verilog regression that leaves a real latch on silicon. Still ALL SYNTHESIZE. Refs #1764