test: CI quantifies 'size costs TIME (microcode steps), not AREA' - #1891
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The emit-bitexact gate now prints, per topology, the microcode step count next to the one-shared-multiplier datapath invariant: (2,2,1)=32 steps -> (2,4,2)=88 -> deep [3,4,4,2,1]=216, while the synth area report shows cells stay ~constant (13945 -> 17468). So the whitepaper's headline claim -- network size costs TIME (microcode steps), not AREA (one shared multiply/add) -- is measured on every PR, not just asserted in prose. The step count also predicts on-silicon timing-marginality (more steps per frame = more chances for a glitch on the timing-relaxed shared-core path), tying the CI metric to the silicon reality from cycles 86-89. Also added [N steps / N regs] to each per-topology bit-exact OK line. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Quantified the whitepaper's headline claim in CI. The emit-bitexact gate now prints, per topology, the microcode step count next to the one-shared-multiplier datapath invariant: (2,2,1)=32 steps → (2,4,2)=88 → deep [3,4,4,2,1]=216, while the synth area report shows cell counts stay ~constant (13945 → 17468). So 'network size costs TIME (microcode steps), not AREA (one shared multiply/add)' is now measured on every PR, not just asserted in prose.
Bonus: the step count also predicts on-silicon timing-marginality — more steps per frame = more chances for a glitch on the timing-relaxed shared-core path (why the generated trainer with trainable biases needed more seed-search). Ties the CI metric to the silicon reality found in cycles 86-89. Also added [N steps / N regs] to each per-topology OK line. Refs #1764