feat: emit_verilog init= -> the verified generator trains XOR on real silicon - #1890
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emit_verilog now takes an optional init dict (default None) that overrides the random
weight init. With an XOR near-solution init, the CI-verified generator emits a
microsequencer that trains XOR (29/30 epochs in the model). This closed the last gap:
the CI-verified generator's RTL now trains a neural net on REAL SILICON (not the
hand-written bpseq.v). emit_verilog(2,2,1,'genbp',clk_div=16,init=XOR) -> UART wrapper
-> seed-searched openXC7 build -> flashed to the AX7203: trains XOR to 4/4, 24/25 (and
21/22) epochs, converging, forward bit-exact to the model at ep0. The generated trainer
(trainable biases -> more microcode steps) is more timing-marginal than the lean bpseq;
needed seed 6 of {1,2,3,6,7,8}. Default emit output byte-identical (CI gate unaffected).
Refs #1764
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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emit_verilognow takes an optionalinitdict (default None) that overrides the random weight init. With an XOR near-solution init, the CI-verified generator emits a microsequencer that trains XOR (29/30 epochs in the model).This closed the last gap: the CI-verified generator's RTL now trains a neural net on REAL SILICON (not the hand-written bpseq.v).
emit_verilog(2,2,1,'genbp',clk_div=16,init=XOR)→ UART wrapper → seed-searched openXC7 build → flashed to the AX7203: trains XOR to 4/4, 24/25 (and 21/22) epochs, converging (y11→0.013), forward bit-exact to the model at ep0. The generated trainer (trainable biases → more microcode steps) is more timing-marginal than the lean bpseq; needed seed 6 of {1,2,3,6,7,8}. Default emit output byte-identical (CI gate unaffected). Refs #1764