feat: extend IGLA RACE cross-target to systolic PE + gen-backend findings - #1881
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…ings verify_igla_race.py now also cross-checks systolic_ternary_pe (psum_out = psum_in + ternary_mul(a,w), i16 accumulator) across C + Rust + reference over 800 vectors incl. edges: C == Rust == reference bit-exact. ternary_mac and the systolic PE are both multi-target-verified. Finding (#1773 concrete in C/Rust): systolic_ternary uses/calls ternary_mul but the import is NOT emitted into its gen-c/gen-rust output -- a dangling reference; the primitive is supplied from ternary_mac's output. Finding (gen-rust): emits psum_in(i16) + prod(i8) with no cast -- Rust rejects the mixed-width add (C promotes); worked around with a documented to cross-check the arithmetic. Wired the systolic spec into the gate trigger. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Extends the IGLA RACE bridge up the datapath.
verify_igla_race.pynow also cross-checkssystolic_ternary_pe(psum_out = psum_in + ternary_mul(a,w), i16 accumulator) across C + Rust + reference over 800 vectors incl. edges (a=-128, invalid codes, i16 psum saturation): C == Rust == reference bit-exact. ternary_mac and the systolic PE are both multi-target-verified.Findings: (1) #1773 concrete in C/Rust —
systolic_ternaryuses + callsternary_mulbut the import is NOT emitted into its gen-c/gen-rust output (dangling reference); the primitive is supplied from ternary_mac's output. (2) gen-rust emitspsum_in(i16) + prod(i8)with no cast — Rust rejects the mixed-width add (C promotes); worked around with a documentedas i16. Wired the systolic spec into the gate trigger. Refs #1764