feat: prove GF-T primitives bit-exact across C + Rust + Verilog + model - #1877
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Strengthens the one-spec-any-target thesis from Verilog-only to four targets.
verify_multitarget.py emits smul/sadd (the exact functions the trainer's shared
datapath uses) via t27c gen-c and gen-rust, compiles both (cc/rustc), and
cross-checks against the independent Python GF-T model over 600 random operand
pairs each: C == model and Rust == model bit-exact for both. Combined with
Verilog == model (verify_emit_bitexact), all of {Verilog, C, Rust, model} agree
bit-for-bit. Wired into emit-bitexact-gate (SKIPs if cc/rustc/t27c absent).
gen-c emits the spec's test blocks as assert_eq() calls undeclared in C; stubbed
as a no-op macro before include since we call the functions directly.
Refs #1764
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Strengthens the one spec → any target, bit-exact thesis from Verilog-only to four targets.
verify_multitarget.pyemitssmul/sadd(the exact functions the trainer's shared datapath uses) via t27cgen-candgen-rust, compiles both (cc/rustc), and cross-checks against the independent Python GF-T model over 600 random operand pairs each: C == model and Rust == model bit-exact for both. Combined with Verilog == model (verify_emit_bitexact), all of {Verilog, C, Rust, model} agree bit-for-bit. Wired into emit-bitexact-gate (SKIPs if cc/rustc/t27c absent). Refs #1764