feat: parametric multi-output/multi-input trainer, proven bit-exact - #1870
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Removes the generator's last functional restriction (n_in=2, n_out=1). emit_verilog
now emits a fully parametric interface: one x{k}i port per input, one t{o}i port
per output, packed yout ([32*n_out-1:0], y0 in LSB word). Every target is driven,
so the uninitialized-t1 divergence the cross-check caught last cycle is impossible.
The bit-exact gate now compares EVERY output per step across 8 topologies including
multi-output (2,2,2)/(2,4,2)/(2,3,3) and multi-input (3,4,2): RTL == model bit-exact
over 80 training steps, all outputs -- the previously-diverging (2,2,2) now passes.
Python self-test adds a (2,4,2) one-hot 2-class classifier that learns (held-out
56/60, argmax over outputs), confirming the multi-output backprop is correct not
just self-consistent. Harness drives via a per-arch task (an inline sequence of many
wait(done) in one initial block hangs under iverilog).
Refs #1764
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Removes the generator's last functional restriction (was n_in=2, n_out=1).
emit_verilognow emits a fully parametric interface: onex{k}iport per input, onet{o}iport per output, packedyout. Every target is driven → the uninitialized-t1 divergence the cross-check caught last cycle is now impossible.The bit-exact gate compares every output per step across 8 topologies incl. multi-output (2,2,2)/(2,4,2)/(2,3,3) and multi-input (3,4,2): RTL == model bit-exact over 80 training steps, all outputs — the previously-diverging (2,2,2) now passes. Python self-test adds a (2,4,2) one-hot classifier that learns (held-out 56/60). Refs #1764